83C694D datasheet(8/33 Pages) SMSC

8 / 33 page

2.2

MANCHESTER ENCODER/

DIFFERENTIAL DRIVER

Data encoding and transmission begins when the

transmit enable input (TXE) goes high and contin-

ues as long as the TXE remains high. It is essential

that the transmit enable and transmit data inputs

meet the setup and hold time requirements for the

rising edge of the transmit clock.

Transmission ends when the transmit enable input

goes low. The last transition occurs at the center of

the bit cell if the last bit is one, or at the boundary

of the bit cell if the last bit is zero.

The AUI differential line driver, which has the ability

to drive up to 50 meters of twisted-pair AUI/Ethernet

transceiver cable, provides the emitter-coupled

logic (ECL) level signals.

With the SEL input, select one of two modes, full-

step or half-step. When SEL is low, TX+ is positive

in relation to TX- in the idle state. When SEL is high,

TX+ and TX- are equal in the idle state. Figures 5-1

through 5-3 illustrate AUI transmit timing. An exter-

nal interface circuit utilizing these signals might

resemble Figure 2-2. In such a configuration, the

transmit interface circuit could utilize an isolation

transformer leading to the 83B692 which would

then drive the coax signal to the network. Another

option would use the AUI connector which would go

to external equipment.

2.3

MANCHESTER DECODER

Decoding is accomplished by a differential input

receiver circuit and an analog phase-locked loop

that separates the Manchester-encoded data

stream into clock signals and NRZ data.

To prevent noise at the AUI RX+ or RX- input from

falsely triggering the decoder, a squelch circuit re-

jects signals with pulse widths less than 20 nsec

(negative going), or with levels less than -175 mV.

When the input exceeds the squelch limits, the

analog phase-locked loop locks onto the incoming

signal and the 83C694D decodes a data frame.

The carrier sense (CRS) is activated, and the re-

ceive data (RXD) and receive clock (RXC) become

available within five bit times. At the end of a frame,

when the normal mid-bit transition on the differential

input ceases, carrier sense is de-activated. The

receive clock remains active for an additional five

bit times. Figures 5-4 through 5-6 illustrate the

receive timing. An external interface circuit for RX+

and RX- might be designed like Figure 2-3.

To avoid signal corruption caused by excessive

voltage fluctuation on the power supply, it is desir-

able to externally implement a voltage regulation

system consisting of a 5.1-volt zener diode. Typi-

cally, as shown in Figure 2-4, the diode’s cathode

is connected to pin 20, pin 23, the VCC side of the

OSR resistor, the VCC side of the BSR resistor, and

a 510

Ω 1⁄4-Watt resistor which goes from the

zener’s cathode to the 12-volt power

supply.

COA

CABL

150Ω 1%

+5V

TX+

TX-

83B692

ETHERNET

TRANSCEIVER

FIGURE 2-2. AUI TRANSMIT PATH

39.2Ω 1%

AUI

CONNECTOR

39.2Ω 1%

0.1µ

0.02µF

0.02µ

RX- or CD-

RX+ or CD+

FIGURE 2-3. AUI RECEIVE PATH

ARCHITECTURE

83C694D

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