ISP1130DL datasheet(42/68 Pages) PHILIPS

42 / 68 page

Philips Semiconductors

ISP1130

USB compound hub with keyboard controller

Objective speciﬁcation

Rev. 01 — 23 March 2000

42 of 68

9397 750 06895

[1]

All bits are individually addressable.

10.7 Watchdog timer

The Watchdog timer is a counter that resets the microcontroller upon overﬂow. This

allows recovery from erroneous processor states (e.g. caused by electrical noise or

RF-interference). To prevent the Watchdog timer from overﬂowing, the software must

reload the counter within a predeﬁned (programmable) time.

The Watchdog timer is a 19-bit counter, consisting of an 11-bit prescaler and an 8-bit

SFR (WDT). The counter is clocked in state 2 of every CPU cycle (= 6 clocks) and

generates a reset when register WDT overﬂows. For a 12 MHz clock frequency, the

interval between overﬂows can be programmed between 1.024 ms (WDT = FFH) and

262.144 ms (WDT = 00H). After a reset the WDT register contains all zeroes.

To enable loading of the Watchdog timer, bit WLE in the PCON register must be set to

logic 1 (see Table 51). When this is done for the ﬁrst time, it also starts the timer. The

Watchdog timer can be disabled by writing 55H to the WDTKEY register, or by a

hardware reset.

Table 67: TCON register: bit allocation

Bit

Symbol

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Reset

000

Access

R/W

Table 68: TCON register: bit description

Bit [1]

Symbol

Description

TCON.7

TF1

Timer 1 overﬂow ﬂag; set by hardware upon Timer 1 overﬂow;

cleared by hardware upon entering the interrupt service routine

TCON.6

TR1

Timer 1 run control bit; 0 = timer OFF, 1 = timer ON

TCON.5

TF0

Timer 0 overﬂow ﬂag; set by hardware upon Timer 0 overﬂow;

cleared by hardware upon entering the interrupt service routine

TCON.4

TR0

Timer 0 run control bit; 0 = timer OFF, 1 = timer ON

TCON.3

IE1

external interrupt 1 ﬂag; set by hardware when a keyboard

interrupt is detected; cleared by hardware upon entering the

interrupt service routine

TCON.2

IT1

triggering mode for external interrupt 1, set by software;

must always be logic 0 (= HIGH-to-LOW transition)

TCON.1

IE0

external interrupt 0 ﬂag; set by hardware when a USB core

interrupt is detected; cleared by hardware upon entering the

interrupt service routine

TCON.0

IT0

triggering mode for external interrupt 0, set by software;

must always be 0 (= HIGH-to-LOW transition)

Table 69: Watchdog timer registers: address mapping

Access

Address (Hex)

WDTKEY

write

WDT

write

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