ISP1130DL datasheet(39/68 Pages) PHILIPS

39 / 68 page

Philips Semiconductors

ISP1130

USB compound hub with keyboard controller

Objective speciﬁcation

Rev. 01 — 23 March 2000

39 of 68

9397 750 06895

10.4 Hub control registers

The hub control registers (Command and Data) are mapped to the external data

memory space of the 80C51 as shown in Table 57. To access these registers use a

MOVX instruction.

10.5 Interrupt structure

The ISP1130 implements a 6-source interrupt structure with 2 priority levels. The

interrupt vector addresses and polling sequence is given in Table 58. The interrupt

priority levels are set via the Interrupt Polarity (IP) register (see Table 61) and the

interrupts can be enabled or disabled via the Interrupt Enable (IE) register (see

Table 59).

External interrupt 0 (EX0) is generated by the USB core when an activity occurs for

any of the three embedded functions. Interrupt EX0 is level-triggered and sets bit IE0

in the TCON register. IE0 is cleared by hardware when the service routine is entered.

External interrupt 1 (EX1) is generated by a key press in the matrix. Interrupt EX1 is

level-triggered and sets bit IE1 in the TCON register. IE1 is cleared by hardware

when the service routine is entered. When the device is in ‘suspend’ state (the

microcontroller clock is disabled), interrupt EX1 is registered and an internal Remote

Wakeup is generated to restart the PLL and the clocks. When the device resumes its

function and the clock to microcontroller core has been restored, the ﬁrmware

branches to the interrupt service routine for EX1.

External interrupt 2 (IN2) is generated by input pin INT, which is edge-triggered

(HIGH-to-LOW transition).

Timer 0 and Timer 1 interrupts are generated by a timer register overﬂow (except for

Timer 0 in Mode 3), signalled by bits TF0 and TF1 in the TCON register. The bit that

generated the interrupt is cleared by hardware, when the service routine is entered.

Table 57: Hub control registers: address mapping

Access

Address (Hex)

Command

write

FFFE

Data

read/write

FFFF

Table 58: Interrupt vectors and polling sequence

Source

Description

Vector address

EX0

external 0 interrupt (USB)

0003H

ET0

timer 0 interrupt

000BH

EX1

external 1 interrupt (keyboard)

0013H

ET1

timer 1 interrupt

001BH

I2C

I2C-bus interrupt

0023H

IN2

external 2 interrupt (input INT)

002BH

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