L800BT90VC datasheet(24/49 Pages) AMD

24 / 49 page

Am29LV800B

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6,

DQ7, and RY/BY#. Table 2 and the following subsec-

tions describe the functions of these bits. DQ7,

RY/BY#, and DQ6 each offer a method for deter-

mining whether a program or erase operation is com-

plete or in progress. These three bits are discussed

first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algorithm is in

progress or completed, or whether the device is in

Erase Suspend. Data# Polling is valid after the rising

edge of the final WE# pulse in the program or erase

command sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to pro-

gramming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid

status information on DQ7. If a program address falls

within a protected sector, Data# Polling on DQ7 is

active for approximately 1 µs, then the device returns

to reading array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the

Erase Suspend mode, Data# Polling produces a “1”

on DQ7. This is analogous to the complement/true

datum output described for the Embedded Program

algorithm: the erase function changes all the bits in a

sector to “1”; prior to this, the device outputs the

“complement,” or “0.” The system must provide an

address within any of the sectors selected for erasure

to read valid status information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximately 100 µs,

then the device returns to reading array data. If not

all selected sectors are protected, the Embedded

Erase algorithm erases the unprotected sectors, and

ignores the selected sectors that are protected.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at

DQ7–DQ0 on the following read cycles. This is

because DQ7 may change asynchronously with DQ0–

DQ6 while Output Enable (OE#) is asserted low.

Fig u re 1 9 , D a ta# Po lling Tim i ngs (Durin g

Embedded Algorithms), in the “AC Characteristics”

section illustrates this.

Table 2 shows the outputs for Data# Polling on DQ7.

Figure 5 shows the Data# Polling algorithm.

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin

that indicates whether an Embedded Algorithm is in

progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# pulse in the

command sequence. Since RY/BY# is an open-drain

output, several RY/BY# pins can be tied together in

parallel with a pull-up resistor to VCC.

DQ7 = Data?

Yes

DQ5 = 1?

Yes

FAIL

PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figure 5. Data# Polling Algorithm

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