COM20020IP3V datasheet(43/82 Pages) SMSC

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Table 12 - Setup 2 Register

BIT

BIT NAME

SYMBOL

DESCRIPTION

Read Bus Timing

Select

RBUSTMG This bit is used to Disable/Enable the High Speed CPU

Read

function

for

High

Speed

CPU

bus

support.

RBUSTMG=0: Disable (Default), RBUSTMG=1: Enable. It

does not influence write operation. High speed CPU Read

operation is only for non-multiplexed bus.

Reserved

This bit is undefined.

5,4

Clock Multiplier

CKUP1, 0

Higher frequency clocks are generated from the 20 MHz

crystal through the selection of these two bits as shown.

This clock multiplier is powered-down on default. After

changing the CKUP1 and CKUP0 bits, the ARCNET core

operation is stopped and the internal PLL in the clock

multiplier is awakened and it starts to generate the 40 MHz.

The lock out time of the internal PLL is 8

μSec typically.

After 1 mS it is necessary to write command data '18H' to

command

for

re-starting

the

ARCNET

core

operation. EF bit must be ‘1’ if the data rate is over 5Mbps.

CAUTION: Changing the CKUP1 and CKUP0 bits must be

one time or less after releasing a hardware reset.

CKUP1

CKUP0

Clock Frequency (Data Rate)

20 MHz (Up to 2.5Mbps) Default

40 MHz (Up to 5Mbps)

Reserved

Note: After changing the CKUP1 or CKUP0 bits, it is

necessary to write a command data '18H' to the command

internal operation is stopped temporarily. The writing of the

command is to start the operation.

These initializing steps are shown below.

Hardware reset (Power ON)

Change CKUP[1, 0] bit

Wait 1mSec (wait until stable oscillation)

Write command '18H' (start internal operation)

Start initializing routine (Execute existing software)

COM20020IP3V Datasheet(PDF) 43 Page - SMSC Corporation

COM20020IP3V Datasheet(HTML) 43 Page - SMSC Corporation

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