COM20020IP3V datasheet(63/82 Pages) SMSC

63 / 82 page

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AD0-AD2,

FIGURE 12 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE

VALID

nCS

VALID DATA

ALE

t2,

D3-D7

nRD

t10

nWR

t11

t12

t13 Note 3

Note 2

ALE High Width

ALE Low Width

nRD Low Width

nRD High Width

nWR

to nRD Low

Parameter

min

max

units

t10

t11

t12

t13

Address Setup to ALE Low

Address Hold from ALE Low

nCS Setup to ALE Low

nCS Hold from ALE Low

ALE Low to nRD Low

nRD Low to Valid Data

nRD High to Data High Impedance

Cycle Time (nRD Low to Next Time Low)

4TARB

MUST BE: RBUSTMG bit = 0

The Microcontroller typically accesses the COM20020 on every other cycle.

Therefore, the cycle time specified in the microcontroller's datasheet

should be doubled when considering back-to-back COM20020 cycles.

Note 1:

TARB is the Arbitration Clock Period

TARB is identical to Topr if SLOW ARB = 0

TARB is twice Topr if SLOW ARB = 1

Topr is the period of operation clock. It depends on CKUP1 and CKUP0 bits

Note 2:

Read cycle for Address Pointer Low/High Registers occurring after a read from

Data Register requires a minimum of 5TARB from the trailing edge of nRD to the

leading edge of the next nRD.

Note 3:

Read cycle for Address Pointer Low/High Registers occurring after a write to

Data Register requires a minimum of 5TARB from the trailing edge of nWR to the

leading edge of nRD.

COM20020IP3V Datasheet(PDF) 63 Page - SMSC Corporation

COM20020IP3V Datasheet(HTML) 63 Page - SMSC Corporation

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