P90CL301 datasheet(22/92 Pages) PHILIPS

22 / 92 page

1996 Dec 11

Philips Semiconductors

Preliminary speciﬁcation

Low voltage 16-bit microcontroller

P90CL301BFH (C100)

7.3

Processing states and exception processing

The P90CL301BFH operates with a maximum internal

clock frequency of 27 MHz down to static operation. Each

clock cycle is divided into 2 states. A non-access machine

cycle has 3 clock cycles or 6 states (S0 to S5). A minimum

bus cycle normally consists of 3 clock cycles (6 states).

When DTACK is not asserted, indicating that data transfer

has not yet been terminated, wait states (WS) are inserted

in multiples of 2.

The CPU is always in one of the four processing states:

• Normal

• Exception

• Halt

• Stopped.

The Normal processing state is associated with instruction

execution; the memory references fetch instructions or

load/save results. A special case of the Normal state is the

Stopped state which is entered by the processor when a

STOP instruction is executed. In this state the CPU does

not make any further memory references.

The Exception state is associated with interrupts, trap

instruction, tracing and other exceptional conditions.

The exception may be generated internally by an

instruction or by any unusual condition arising during the

execution of an instruction. Externally, exception

processing can be forced by an interrupt or by reset.

The halted processing state is an indication of a

catastrophic hardware failure. For example, if during

exception processing of a bus error another bus error

occurs, the CPU assumes that the system is unusable and

halts. Only an external reset can restart a halted

processor. Note that a CPU in the stopped state is not in

the halted state or vice versa.

The Supervisor can work in the User or Supervisor state

determined by the state of bit S in the Status Register.

Accesses to the on-chip peripherals are achieved in the

Supervisor state.

All exception processing is performed in the Supervisor

state once the current contents of the Status Register has

been saved. Then the exception vector number is

determined and copies of the Status Register, the program

counter and the format/vector number are saved on the

Supervisor stack using the Supervisor Stack Pointer

(SSP). Finally the contents of the exception vector location

is fetched and loaded into the Program Counter (PC).

7.3.1

REFERENCE CLASSIFICATION

When the processor makes a reference, it classifies the

kind of reference being made, using the encoding of the

three function code internal lines. This allows external

translation of addresses, control of access, and

differentiation of special processor states, such as

interrupt acknowledge. Table 21 shows the classification

of references.

Table 21 Reference classiﬁcation

7.3.2

EXCEPTION VECTORS

Exception vectors are memory locations from where the

CPU fetches the address of a routine that will handle that

exception. All exception vectors are 2 words long, except

for the reset vector which consists of 4 words, containing

the PC and the SSP. All exception vectors are in the

Supervisor Data space.

A vector number is an 8-bit number which, multiplied by 4,

gives the address of an exception vector. Vector numbers

are generated internally. The memory map for the

exception vectors is shown in the Table 22.

FUNCTION CODE

REFERENCE CLASS

FC2

FC1

FC0

unassigned

User Data

User Program

unassigned

Supervisor Data

Supervisor Program

interrupt acknowledge

P90CL301 Datasheet(PDF) 22 Page - NXP Semiconductors

P90CL301 Datasheet(HTML) 22 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92

Datasheet Download

Link URL