Data Sheet

ADPL13602

analog.com

Rev. 0

21 of 28

Power Dissipation

At a particular operating condition, the power losses that lead to temperature rise of the part are estimated as

follows:

PLOSS = (POUT × (

1

η

− 1)) − (

IOUT2 × RDCR)

POUT = VOUT × IOUT

where:

POUT = Output power

η = Efficiency of the converter

RDCR = DC resistance of the inductor (see the Typical Performance Characteristics for more information on efficiency

at typical operating conditions).

For a typical multilayer board, the thermal performance metrics for the package are as follows:

θJA= 38°C/W

θJC= 4°C/W

The junction temperature of the device can be estimated at any given maximum ambient temperature (TA(MAX)) from

the following equation:

TJ(MAX) = TA(MAX) + (θJA × PLOSS)

If the application has a thermal-management system that ensures that the exposed pad of the device is maintained

at a given temperature (TEP(MAX)) by using proper heat sinks, then the junction temperature of the device can be

estimated at any given maximum ambient temperature as:

TJ(MAX) = TEP(MAX) + (θJC × PLOSS)

Note: Junction temperatures greater than +125°C degrade operating lifetimes.

Printed Circuit Board (PCB) Layout Guidelines

All connections carrying pulsed currents must be very short and as wide as possible. The inductance of these

connections must be kept to an absolute minimum due to the high di/dt of the currents. Since the inductance of a

current-carrying loop is proportional to the area enclosed by the loop, if the loop area is made very small,

inductance is reduced. Additionally, small-current loop areas reduce radiated Electromagnetic Interference (EMI).

A ceramic input filter capacitor should be placed close to the VIN pins of the IC. This eliminates as many trace

inductance effects as possible and gives the IC a cleaner voltage supply. A bypass capacitor for the VCCpin should

also be placed close to the pin to reduce the effects of trace impedance.

When routing the circuitry around the IC, the signal ground and the power ground for switching currents must be

kept separate. They should be connected at a point where switching activity is minimal. This helps to keep the

signal ground quiet. The power ground plane should be kept continuous (unbroken) as far as possible. No trace

carrying a high switching current should be placed directly over any ground plane discontinuity.

PCB layout also affects the thermal performance of the design. A number of thermal throughputs or vias that

connect to a large plane should be provided under the exposed pad of the device for efficient heat dissipation.

For a sample layout that ensures first-pass success, refer to the ADPL13602 evaluation kit layout available

at www.analog.com.