TMS320DM647 datasheet(110/166 Pages) TI

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VPxCLKINx

VPxCLKOUTx

[VCLK2P=0]

VPxCLKOUTx

(Inverted)

[VCLK2P=1]

VPxCTLx,V

PxD[19:0]

(Outputs)

VPxCTLx

(Input)

TMS320DM647/TMS320DM648

Digital Media Processor

SPRS372 – MAY 2007

Table 6-40. Switching Characteristics Over Recommended Operating Conditions in Video Display Mode

for Video Data and Control Output Shown With Respect to VPxCLKINx and VPxCLKOUTx

(1) (2)

(see Figure 6-24)

-720

-900

NO.

PARAMETER

UNIT

MIN

MAX

tc(VKO)

Cycle time, VPxCLKOUTx

V – 0.7

V + 0.7

tw(VKOH)

Pulse duration, VPxCLKOUTx high

VH – 0.7

VH + 0.7

tw(VKOL)

Pulse duration, VPxCLKOUTx low

VL – 0.7

VL + 0.7

tt(VKO)

Transition time, VPxCLKOUTx

1.8

td(VKIH-VKOH)

Delay time, VPxCLKINx high to VPxCLKOUTx high(3)

1.1

5.7

td(VKIL-VKOL)

Delay time, VPxCLKINx low to VPxCLKOUTx low(3)

1.1

5.7

td(VKIH-VKOL)

Delay time, VPxCLKINx high to VPxCLKOUTx low

1.1

5.7

td(VKIL-VKOH)

Delay time, VPxCLKINx low to VPxCLKOUTx high

1.1

5.7

td(VKIH-VPOUTV)

Delay time, VPxCLKINx high to VPxOUT valid(4)

td(VKIH-VPOUTIV)

Delay time, VPxCLKINx high to VPxOUT invalid(4)

1.7

td(VKOH-VPOUTV)

Delay time, VPxCLKOUTx high to VPxOUT valid(1)(4)

4.3

td(VKOH-VPOUTIV)

Delay time, VPxCLKOUTx high to VPxOUT invalid(1)(4)

–0.2

Figure 6-24. Video Port Display Data Output Timing and Control Input/Output Timing With Respect to

VPxCLKINx and VPxCLKOUTx

(1)

V = the video input clock (VPxCLKINx) period in ns.

(2)

VH is the high period of V (video input clock period) in ns and VL is the low period of V (video input clock period) in ns.

(3)

Assuming non-inverted VPxCLKOUTx signal.

(4)

VPxOUT consists of VPxCTLx and VPxD[19:0]

110

Peripheral Information and Electrical Specifications

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