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PCD5032 Datasheet(PDF) 14 Page - NXP Semiconductors |
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PCD5032 Datasheet(HTML) 14 Page - NXP Semiconductors |
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14 / 24 page ![]() 1997 Apr 03 14 Philips Semiconductors Product specification ADPCM CODEC for digital cordless telephones PCD5032 10 DC AND AC CHARACTERISTICS VDD = 2.7 to 5.5 V; VSS = 0 V; CLK = 3456 kHz; Tamb = −25 to +70 °C; all voltages with respect to VSS; unless otherwise specified. Specifications valid in active mode, except standby supply current. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT General VDD operating supply voltage 2.7 − 5.5 V IDD operating supply current no load; Tamb =25°C; note 1 − 714 mA Istb standby supply current Tamb =25°C; note 1 − 20 100 µA ILI input leakage current VSS ≤ VI ≤ VDD −1 − +1 µA VGA analog signal ground voltage 0.48VDD 0.5VDD 0.52VDD V VREF+ positive reference voltage note 2 0.8 1.0 1.2 V VREF− negative reference voltage note 2 −0.8 −1.0 −1.2 V Digital I/O VIL LOW level input voltage note 3 0 − 0.3VDD V VIH HIGH level input voltage note 3 0.7VDD − VDD V VOL LOW level output voltage note 3 −− 0.4 V VOH HIGH level output voltage note 3 VDD −o.4 − VDD V Rpd(int) internal pull-down resistance note 3 − 150 − k Ω fDCLK DCLK frequency note 4 1 ⁄54fCLK =64 − fCLK kHz fRAS, fTAS RAS, TAS frequency note 4 − 8 − kHz I2C-bus timing fSCL SCL clock frequency −− 100 kHz tSW tolerable pulse spike width −− 50 ns tBUF bus free time 4.7 −−µs tSU;STA set-up time repeated START 4.7 −−µs tHD;STA hold time START condition 4.0 −−µs tLOW SCL LOW time 4.7 −−µs tHIGH SCL HIGH time 4.0 −−µs tr rise time SDA and SCL −− 1.0 µs tf fall time SDA and SCL −− 0.3 µs tSU;DAT data set-up time 250 −− ns tHD;DAT data hold time 0 −− ns tSU;STO set-up time STOP condition 4.0 −−µs Analog inputs; note 5 Zi(TM+) input impedance, TM+ note 6 − 125 − k Ω Zi(TM−) input impedance, TM − note 6 − 125 − k Ω Vi nominal input level RMS value; note 7 − 12 − mV Vi(max) maximum input signal RMS value; note 8 − 56 − mV Gv(min) minimum voltage gain −4 −3 −2dB Gv(max) maximum voltage gain +3 +4 +5 dB |
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