LTM4680 datasheet(20/36 Pages) AD

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LTM4650-2

Rev. 0

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APPLICATIONS INFORMATION

Solving for temperature:

T(KELVIN)=

∆VD

K'D

(

ｰCELSIUS)= T(KELVIN)– 273.15

where

300°K = 27°C

means that is we take the difference in voltage across the

diode measured at two currents with a ratio of 10, the

resulting voltage is 198μV per Kelvin of the junction with

a zero intercept at 0 Kelvin.

The diode-connected PNP transistor at the TEMP pin

can be used to monitor the internal temperature of the

LTM4650-2. See Figure 25 for an example.

Improve Transient Response and Reduce Output

Capacitance with AVP

Fast load transient response, limited board space and low

cost are requirements of microprocessor power supplies.

Active voltage positioning improves transient response

and reduces the output capacitance required to power a

microprocessor, where in this case, a typical load step can

be from 0A to 12.5A in 1μs or 12.5A to 0A in 1μs.

Active voltage positioning is a form of deregulation. It sets

the output voltage high for light loads and low for heavy

loads. When the load current suddenly increases, the out-

put voltage starts from a level higher than the nominal,

so the output voltage can drop more and stay within the

specified voltage range. When the load current suddenly

decreases, the output voltage starts at a level lower than

the nominal, so the output voltage can have more over-

shoot and stay within the specified voltage range. Less

output capacitance is required when voltage positioning

is used because more voltage variation is allowed on the

output capacitors.

Figure 30 and Figure 32 show the voltage regulator with-

out AVP and with AVP. The load transient response before

and after AVP implementation are shown on Figure 31

and Figure 33. On the design with AVP, the output volt-

age swings from 1.05V at minimum load to 0.95V at full

load. The transient performance has been improved, while

using fewer output capacitors.

The Analog Devices design tool (LTpowerCAD) will be

provided for AVP applications.

Thermal Considerations and Output Current Derating

The thermal resistances reported in the Pin Configuration

section of the data sheet are consistent with those param-

eters defined by JESD51-9 and are intended for use with

finite element analysis (FEA) software modeling tools that

leverage the outcome of thermal modeling, simulation,

and correlation to hardware evaluation performed on a

µModule package mounted to a hardware test board—

also defined by JESD51-9 (Test Boards for Area Array

Surface Mount Package Thermal Measurements). The

motivation for providing these thermal coefficients is

found in JESD 51-12 (Guidelines for Reporting and Using

Electronic Package Thermal Information).

Many designers may opt to use laboratory equipment and

a test vehicle such as the demo board to anticipate the

µModule regulator’s thermal performance in their appli-

cation at various electrical and environmental operating

conditions to compliment any FEA activities. Without

FEA software, the thermal resistances reported in the

Pin Configuration section are in-and-of themselves not

relevant to providing guidance on thermal performance;

instead, the derating curves provided in the data sheet can

be used in a manner that yields insight and guidance per-

taining to one’s application-usage, and can be adapted to

correlate thermal performance to one’s own application.

The Pin Configuration section typically gives four thermal

coefficients explicitly defined in JESD 51-12; these coef-

ficients are quoted or paraphrased as follows:

1. θJA, the thermal resistance from junction to ambi-

ent, is the natural convection junction-to-ambient air

thermal resistance measured in one cubic foot sealed

enclosure. This environment is sometimes referred to

as “still air”, although natural convection causes the

air to move. This value is determined with the part

mounted to a JESD 51-9 defined test board, which

does not reflect an actual application or viable operat-

ing condition.

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