6.6 I2C Interface Timing

minimum and maximum specifications are over –40 °C to 125 °C and V+ = 1.14 V to 5.5 V (unless otherwise noted)(1)

FAST MODE

FAST MODE PLUS

UNIT

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency

1

400

1

1000

kHz

t(BUF)

Bus-free time between STOP and START conditions

0.6

0.5

µs

t(SUSTA)

Repeated START condition setup time

0.6

0.26

µs

t(HDSTA)

Hold time after repeated START condition.

After this period, the first clock is generated.

0.6

0.26

µs

t(SUSTO)

STOP condition setup time

0.6

0.26

µs

t(HDDAT)

Data hold time(2)

100

900

12

150

ns

t(SUDAT)

Data setup time

100

50

ns

t(LOW)

SCL clock low period

1.3

0.5

µs

t(HIGH)

SCL clock high period

0.6

0.26

µs

t(VDAT)

Data valid time (data response time)(3)

0.9

0.45

µs

tR

SDA, SCL rise time

300

120

ns

tF

SDA, SCL fall time

300

20 x

(V+ / 5.5 V)

120

ns

ttimeout

Timeout (SCL = GND or SDA = GND)

30

30

ms

tLPF

Glitch suppression filter

50

50

ns

(1)

The controller and device have the same V+ value. Values are based on statistical analysis of samples tested during initial release.

(2)

The maximum t(HDDAT) can be 0.9 µs for fast mode, and is less than the maximum t(VDAT) by a transition time.

(3)

t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).

SCL

SDA

t

(LOW)

t

R

t

F

t

(HDSTA)

t

(HDSTA)

t

(HDDAT)

t

(BUF)

t

(SUDAT)

t

(HIGH)

t

(SUSTA)

t

(SUSTO)

P

S

S

P

Figure 6-1. Two-Wire Timing Diagram

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TMP110

SNIS233 – FEBRUARY 2024

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