AT90USB646 datasheet(262/435 Pages) ATMEL

262 / 435 page

262

7593D–AVR–07/06

AT90USB64/128

Figure 21-16. Plug-in Detection Input Block Diagram

The control logic of the UVBUS pad outputs 2 signals:

• The “session_valid” signal is active high when the voltage on the UVBUS pad is higher or

equal to 1.4V.

• The “Va_Vbus_valid” signal is active high when the voltage on the UVBUS pad is higher or

equal to 4.4V.

In the Host mode, the VBUS flag follows the next hysteresis rule:

• VBUS is set when the voltage on the UVBUS pad is higher or equal to 4.4 V.

• VBUS is cleared when the voltage on the UVBUS pad is lower than 1.4 V.

In the Peripheral mode, the VBUS flag follows the next rule:

• VBUS is set when the voltage on the UVBUS pad is higher or equal to 1.4 V.

• VBUS is cleared when the voltage on the UVBUS pad is lower than 1.4 V.

The VBUSTI interrupt is triggered at each transition of the VBUS flag.

21.11 ID detection

The ID pin transition is detected thanks to the following architecture:

Figure 21-17. ID Detection Input Block Diagram

The ID pin can be used to detect the USB mode (Peripheral or Host) or software selected. This

allows the UID pin to be used has general purpose I/O even when USB interface is enable.

When the UID pin is selected, by default, (no A-plug or B-plug), the macro is in the Peripheral

VBUSTI

USBINT.0

UVBUS

VBUS

USBSTA.0

VSS

VDD

Pad logic

Logic

Session_valid

Va_Vbus_valid

VBus_pulsing

VBus_discharge

UIMOD

UHWCON.7

UID

USBSTA.1

Internal Pull Up

VDD

UIDE

UHWCON.6

AT90USB646 Datasheet(PDF) 262 Page - ATMEL Corporation

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