AT90USB646 datasheet(264/435 Pages) ATMEL

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7593D–AVR–07/06

AT90USB64/128

Set to disable the clock inputs (the ”Resume Detection” is still active). This reduces the power

consumption. Clear to enable the clock inputs.

• 4 – OTGPADE: OTG Pad Enable

Set to enable the OTG pad. Clear to disable the OTG pad.

Note that this bit can be set/cleared even if USBE=0 (this allows the VBUS detection even if the

USB macro is disable).

• 3-2 – Reserved

The value read from these bits is always 0. Do not set these bits.

• 1 – IDTE: ID Transition Interrupt Enable Bit

Set this bit to enable the ID Transition interrupt generation. Clear this bit to disable the ID Transi-

tion interrupt generation.

• 0 – VBUSTE: VBUS Transition Interrupt Enable Bit

Set this bit to enable the VBUS Transition interrupt generation.

Clear this bit to disable the VBUS Transition interrupt generation.

• 7-4 - Reserved

The value read from these bits is always 0. Do not set these bits.

• 3 – SPEED: Speed Status Flag

This should be read only when the USB controller operates in host mode, in device mode the

value read from this bit is underterminate.

Set by hardware when the controller is in FULL-SPEED mode. Cleared by hardware when the

controller is in LOW-SPEED mode.

• 2 – Reserved

The value read from this bit is always 0. Do not set this bit.

• 1 – ID: IUD pin Flag

The value read from this bit indicates the state of the UID pin.

• 0 – VBUS: VBus Flag

The value read from this bit indicates the state of the UVBUS pin. This bit can be used in device

mode to monitor the USB bus connection state of the appication. See Section 21.10, page 261

for more details.

Bit

7654

----

SPEED

VBUS

USBSTA

Read/Write

RRRR

Initial Value

0000

Bit

76543210

------

IDTI

VBUSTI

USBINT

Read/Write

RRRRRR

R/W

AT90USB646 Datasheet(PDF) 264 Page - ATMEL Corporation

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