TSL25721 datasheet(18/41 Pages) OSRAM

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Datasheet, Public

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[v2-00] 2022-Nov-30

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TSL2572 − Principles Of Operation

System State Machine Timing

The system state machine shown in Figure 16 provides an

overview of the states and state transitions that provide system

control of the device. This section highlights the programmable

features, which affect the state machine cycle time, and

provides details to determine system level timing.

When the power management feature is enabled (WEN), the

state machine will transition in turn to the Wait state. The wait

time is determined by WLONG, which extends normal operation

by 12× when asserted, and WTIME. The formula to determine

the wait time is given in the box associated with the Wait state

in Figure 19.

When the ALS feature is enabled (AEN), the state machine will

transition through the ALS Init and ALS ADC states. The ALS Init

state takes 2.73 ms, while the ALS ADC time is dependent on

the integration time (ATIME). The formula to determine ALS ADC

time is given in the associated box in Figure 19. If an interrupt

is generated as a result of the ALS cycle, it will be asserted at

the end of the ALS ADC state and transition to the Sleep state

if SAI is enabled.

Figure 19:

Detailed State Diagram

Note(s):

1. PON, WEN, AEN, and SAI are fields in the Enable register (0x00).

Wait

Sleep

Idle

WTIME: 1 ~ 256 steps

WLONG = 0

WLONG = 1

Time:

2.73 ms/step

32.8 ms/step

Range:

2.73 ms ~ 699 ms

32.8 ms ~ 8.39s

Time: 2.73 ms

ATIME: 1 ~ 256 steps

Time: 2.73 ms/step

Range: 2.73 ms ~ 699 ms

INT & SAI

!PON

I2C Start

ALS

Init

WEN

& AEN

ALS

ADC

!WEN

& AEN

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