The circuit accepts single-ended or differential input signals. The PGA849 operates with independent input and

output power supplies. In this example, ±15V power supplies are used to power the input-stage, and a unipolar

5.3V supply powers the output-stage. The PGA849 output stage supply is powered by the same 5.3V ADC

supply. The 5.3V output supply operation prevents overloading the ADC inputs during PGA overdrive conditions.

The REF6250 is selected as the ADC voltage reference. The REF6250 is a low-noise, low-drift, precision, 5V

reference connected to the ADS8860 reference input ADC REFIN pin.

The PGA849 output voltage is developed with respect to the REF pin. The REF pin is set to the SAR ADC

midscale voltage by dividing the REF6250 ADC reference with a precision resistive voltage divider. The OPA192

buffer drives the PGA849 REF pin. The OPA192 is a precision amplifier with low offset, low drift and 10MHz

bandwidth.

8.2.1.1 Design Requirements

The design requirements for the application driving the ADS8860 ADC are listed in the following table.

Table 8-1. Design Parameters

PARAMETER

VALUE

Supply voltages

VS± = ±15V, LVDD = 5.3V, LVSS = GND, ADC REFIN = 5V,

PGA REF = 2.5V

Full-scale range of ADC

FSR = 5V

Sampling rate of ADC

fSAMPLE = 1MSPS

PGA gain

0.125, 0.25, 0.5, 1, 2,4, 8, 16

Input voltages (VPP, differential)

25V, 16V, 8V, 4V, 2V, 1V, 0.5V, 0.25V

Signal frequency

1kHz

RC kickback filter

RFIL = 15Ω, CDIFF = 1.2nF, CCM = 120pF

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PGA849

SBOSAG3 – MARCH 2024

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