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AD9869BCPZ Datasheet(PDF) 13 Page - Analog Devices

Part # AD9869BCPZ
Description  Broadband Modem Mixed-Signal Front End
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9869BCPZ Datasheet(HTML) 13 Page - Analog Devices

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AD9869
Rev. 0 | Page 13 of 36
Power-Up Default Value
MODE = 0
(Half-Duplex)
MODE = 1
(Full-Duplex)
Address
(Hex)
Bit1
Description
Width
CONFIG = 0
CONFIG = 1
CONFIG = 0
Comments
Tx/Rx PATH GAIN CONTROL
0x09
6
Enable SPI Rx Gain
1
0x00
0x00
0x00
5:0
Rx Gain Code
6
0x00
0x00
0x00
Default setting is for hardware Rx gain
code via PGA or Tx data port.
0x0A
6
Enable SPI Tx Gain
1
0x7F
0x7F
0x7F
5:0
Tx Gain Code
6
0x7F
0x7F
0x7F
Default setting is for Tx gain code via
SPI control.
TxPGA AND RxPGA CONTROL
0x0B
6
PGA Code for Tx
1
0
0
0
5
PGA Code for Rx
1
1
1
1
3
Force Gain Strobe
1
0
0
0
2
Rx Gain on Tx Port
1
0
0
1
1
3-Bit RxPGA Port
1
0
1
0
Default setting is RxPGA control active via
PGA port.
Tx DIGITAL FILTER AND INTERFACE
0x0C
7:6
Interpolation
Factor
2
01
00
01
4
Invert
TXEN/TXSYNC
1
0
0
0
3
Tx 5/5 Nibble2
1
N/A
N/A
0
2
LS Nibble First2
1
N/A
N/A
0
1
TXCLK Neg. Edge
1
0
0
0
0
Twos Complement
1
0
0
1
Default setting is 2× interpolation with
LPF response. Data format is straight
binary for half-duplex and twos
complement for full-duplex interface.
Rx INTERFACE AND ANALOG/DIGITAL LOOPBACK
0x0D
7
Analog Loopback
1
0
0
0
6
Digital Loopback2
1
0
0
0
5
Rx Port Three-State
1
N/A
N/A
0
4
Invert
RXEN/RXSYNC
1
0
0
0
3
Rx 5/5 Nibble
1
N/A
N/A
0
2
LS Nibble First
1
N/A
N/A
0
1
RXCLK Neg. Edge
1
0
0
0
0
Twos Complement
1
0
0
1
Data format is straight binary for
half-duplex and twos complement for
full-duplex interface. Analog loopback:
ADC Rx data fed back to TxDAC. Digital
loopback: Tx input data to Rx output port.
DIGITAL OUTPUT DRIVE STRENGTH, TxDAC OUTPUT, AND REV ID
0x0E
7
Low Digital Drive
Strength
1
0
0
0
0
TxDAC Output
1
0
0
0
Default setting is for high drive strength
and IAMP enabled.
0x0F
3:0
REV ID Number
4
0x00
0x00
0x00
Tx IAMP GAIN AND BIAS CONTROL
0x10
7
Select Tx Gain
1
0x04
0x04
0x04
2:0
N
3
0x04
0x04
0x04
N = 0, 1, 2, 3, 4.
0x12
6:4
Standing Current
3
0x01
0x01
0x01
Standing current.
2:0
IOFF1 Standing
Current
3
0x01
0x01
0x01
7:5
CPGA Bias Adjust
3
4:3
SPGA Bias Adjust
2
0x13
2:0
ADC Bias Adjust
4
0x00
0x00
0x00
Current bias setting for Rx path’s
functional blocks. Refer to the Power
Reduction Options section.
1 Bits that are undefined should always be assigned a 0.
2 Full-duplex only.



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