AD9869BCPZ datasheet(19/36 Pages) AD

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AD9869

Rev. 0 | Page 19 of 36

RxPGA CONTROL

The AD9869 contains a digital PGA in the Rx path that is used

to extend the dynamic range. The RxPGA can be programmed

over −12 dB to +48 dB with 1 dB resolution using a 6-bit word,

and with a 0 dB setting corresponding to a 2 V p-p input signal.

The 6-bit word is fed into a look-up table (LUT) that is used to

distribute the desired gain over three amplification stages within

the Rx path. Upon power-up, the RxPGA gain register is set to

its minimum gain of −12 dB. The RxPGA gain mapping is

shown in Figure 15.

6-BIT DIGITAL WORD-DECIMAL EQUIVALENT

–12

–6

612

Figure 15. Digital Gain Mapping of RxPGA

Table 15 lists the SPI registers pertaining to the RxPGA.

Table 15. SPI Registers for RxPGA Control

Address

(Hex)

Bit

Description

0x09

Enable RxPGA update via SPI.

5:0

RxPGA gain code.

0x0B

Select TxPGA via PGA[5:0].

Select RxPGA via PGA[5:0].

Enable software gain strobe, full-duplex.

Enable RxPGA update via Tx[5:0], full-duplex.

3-Bit RxPGA gain mapping, half-duplex.

The RxPGA gain register can be updated via the Tx[5:0] port,

the PGA[5:0] port, or the SPI port. The first two methods allow

fast updates of the RxPGA gain register and should be considered

for digital AGC functions requiring a fast closed-loop response.

The SPI port allows direct update and readback of the RxPGA

gain register via Register 0x09 with an update rate limited to 1.6

MSPS (with SCLK = 32 MHz). Note that Bit 6 of Register 0x09

must be set for a read or write operation.

Updating the RxPGA via the Tx[5:0] port is an option only in

full-duplex mode1. In this case, a high level on the GAIN pin2

with TXSYNC low programs the PGA setting on either the

rising edge or falling edge of RXCLK, as shown in Figure 16.

The GAIN pin must be held high, TXSYNC must be held low,

and gain data must be stable for one or more clock cycles to

update the RxPGA gain setting.

A low level on the GAIN pin enables data to be fed to the digital

interpolation filter. This interface should be considered when

upgrading existing designs from the AD9875/AD9876 MxFE

products or from half-duplex applications trying to minimize

an ASIC pin count.

tSU

RXCLK

TXSYNC

Tx[5:0]

tHD

GAIN

Figure 16. Updating RxPGA via Tx[5:0] in Full-Duplex Mode

Updating the RxPGA (or TxPGA) via the PGA[5:0] port is

an option for both the half-duplex3 and full-duplex interface.

The PGA port consists of an input buffer that passes the 6-bit

data appearing at its input directly to the RxPGA (or TxPGA)

gain register with no gating signal required. Bit 5 or Bit 6 of

RxPGA or TxPGA gain register. In applications that switch

between RxPGA and TxPGA gain control via PGA[5:0], be

sure that the RxPGA (or TxPGA) is not inadvertently loaded

with the wrong data during a transition. In the case of an

RxPGA-to-TxPGA transition, first deselect the RxPGA gain

setting, and then select the TxPGA gain register.

Note that a silicon bug exists with the full-duplex interface

(MODE = 1), which requires that the GAIN/PGA[5] pin

remains low for the digital Tx path to remain enabled. Full-

duplex protocol applications must use the SPI port to control

the Tx and Rx gain. Half-duplex protocol applications using the

function can use an AND gate with TXQUIET and the PGA5

bit serving as inputs to ensure that the GAIN/PGA[5] pin

remains low during a Tx operation.

1 Default setting for full-duplex mode (MODE = 1).

2 The gain strobe can also be set in software via Register 0x0B, Bit 3 for

continuous updating. This eliminates the requirement for the external gain

signal, reducing the ASIC pin count by 1.

3 Default setting for half-duplex mode (MODE = 0).

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