M29F800DT datasheet(12/53 Pages) STMICROELECTRONICS

12 / 53 page

Signal descriptions

M29F800DT

12/53

Signal descriptions

See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals

connected to this device.

2.0.1

Address Inputs (A0-A18)

The Address Inputs select the cells in the memory array to access during Bus Read

operations. During Bus Write operations they control the commands sent to the Command

Interface of the internal state machine.

2.0.2

Data Inputs/Outputs (DQ0-DQ7)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operation. During Bus Write operations they represent the commands sent to the Command

Interface of the internal state machine.

2.0.3

Data Inputs/Outputs (DQ8-DQ14)

The Data Inputs/Outputs output the data stored at the selected address during a Bus Read

operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are

high impedance. During Bus Write operations the Command Register does not use these

bits. When reading the Status Register these bits should be ignored.

2.0.4

Data Input/Output or Address Input (DQ15A-1)

When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).

When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the

LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout

the text consider references to the Data Input/Output to include this pin when BYTE is High

and references to the Address Inputs to include this pin when BYTE is Low except when

stated explicitly otherwise.

2.0.5

Chip Enable (E)

The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to

be performed. When Chip Enable is High, VIH, all other pins are ignored.

2.0.6

Output Enable (G)

The Output Enable, G, controls the Bus Read operation of the memory.

2.0.7

Write Enable (W)

The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface.

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