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PHN205 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # PHN205
Description  Dual N-channel enhancement mode MOS transistor
PDF  12 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

PHN205 Datasheet(HTML) 2 Page - NXP Semiconductors

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1997 Oct 22
2
Philips Semiconductors
Product specification
Dual N-channel enhancement mode
MOS transistor
PHN205
FEATURES
• High-speed switching
• No secondary breakdown
• Very low on-state resistance.
APPLICATIONS
• Motor and actuator driver
• Power management
• Synchronized rectification.
DESCRIPTION
Two N-channel enhancement mode MOS transistors in an
8-pin plastic SOT96-1 (SO8) package.
CAUTION
The device is supplied in an antistatic package.
The gate-source input must be protected against static
discharge during transport or handling.
PINNING - SOT96-1 (SO8)
PIN
SYMBOL
DESCRIPTION
1s1
source 1
2g1
gate 1
3s2
source 2
4g2
gate 2
5d2
drain 2
6d2
drain 2
7d1
drain 1
8d1
drain 1
Fig.1 Simplified outline and symbol.
handbook, halfpage
d
MAM117
1
4
5
8
g
s
d
1
1
1
1
d
g
s
d
2
2
2
2
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
Per N-channel
VDS
drain-source voltage (DC)
−
30
V
VSD
source-drain diode forward voltage
IS = 1.25 A
−
1V
VGS
gate-source voltage (DC)
−±20
V
VGSth
gate-source threshold voltage
ID = 1 mA; VDS =VGS
1
2.8
V
ID
drain current (DC)
Ts =80 °C
−
6.4
A
RDSon
drain-source on-state resistance
ID = 3.2 A; VGS =10V
−
50
m
Ω
Ptot
total power dissipation
Ts =80 °C
−
3.5
W



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