SC101161DT datasheet(122/142 Pages) FREESCALE

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Device User Guide — 9S12DT128DGV2/D V02.15

122

Freescale Semiconductor

Figure A-3 Basic PLL functional diagram

The following procedure can be used to calculate the resistance and capacitance values using typical

values for K1, f1 and ich from (Table A-16).

The grey boxes show the calculation for fVCO = 50MHz and fref = 1MHz. E.g., these frequencies are used

for fOSC = 4MHz and a 25MHz bus clock.

The VCO Gain at the desired VCO frequency is approximated by:

The phase detector relationship is given by:

ich is the current in tracking mode.

The loop bandwidth fC should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,

typical values are 50.

ζ = 0.9 ensures a good transient response.

fosc

refdv+1

fref

Phase

Detector

VCO

synr+1

fvco

Loop Divider

KΦ

∆

fcmp

VDDPLL

XFC Pin

1 e

vco

–

()

⋅

-----------------------

⋅

100

–

()

100

–

------------------------

⋅

= -90.48MHz/V

KΦ

–

⋅

= 316.7Hz/

Ω

ζ f

ref

⋅⋅

πζ





⋅

------------------------------------------

------

ref

410

⋅

--------------

ζ 0.9

()

;

→

fC < 25kHz

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