SC101161DT datasheet(123/142 Pages) FREESCALE

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Device User Guide — 9S12DT128DGV2/D V02.15

123

Freescale Semiconductor

And finally the frequency relationship is defined as

With the above values the resistance can be calculated. The example is shown for a loop bandwidth

fC=10KHz:

The capacitance Cs can now be calculated as:

The capacitance Cp should be chosen in the range of:

A.5.3.2 Jitter Information

The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock fcmp, the

deviation from the reference clock fref is measured and input voltage to the VCO is adjusted

accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.

Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock

jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.

VCO

ref

-------------

synr

()

⋅

= 50

π nf

⋅⋅ ⋅

KΦ

-----------------------------

= 2*

π*50*10kHz/(316.7Hz/Ω)=9.9kΩ =~ 10kΩ

⋅

π f

C R

⋅⋅

----------------------

0.516

C R

⋅

---------------

ζ 0.9

()

;

≈

= 5.19nF =~ 4.7nF

s 20

⁄

s 10

⁄

≤≤

Cp = 470pF

SC101161DT Datasheet(PDF) 123 Page - Freescale Semiconductor, Inc

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