MAC7101 datasheet(28/56 Pages) FREESCALE

28 / 56 page

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Electrical Characteristics

Freescale Semiconductor

3.10.3 ATD Timing Specifications

Figure 10. ATD External Trigger Timing Diagram

Table 31. ATD External Trigger Timing Specifications

Num C

Parameter

Symbol

Min

Max

Unit

D ETRIG Period (Level-Sensitive Trigger Mode)

TPERIOD 1 + NCONVn

NOTES:

1. NCONVn denotes 8- or 10-bit conversion time (refer to specifications N4, N5, P4 and P5). In order to achieve the

minimum period between conversions when using level-sensitive triggering, ETRIG must remain asserted this long.

—

fATDCLK Cycles

D ETRIG Minimum Pulse Width

Edge-Sensitive Trigger Mode

Level-Sensitive Trigger Mode

tPW

—

fATDCLK Cycles

D ETRIG Level Recovery 2

2. Time prior to the end of a conversion that ETRIG must be negated in order to prevent the start of another conversion.

tLR

1—

fATDCLK Cycles

D Conversion Start Delay

tDLY

—2

fATDCLK Cycles

Level Sensitive

Low Active

Sequence

Conversion Activity

Complete Flag

Low Active

Sequence

Complete Flag

Conversion Activity

Level Sensitive

Falling Edge Active

Conversion Activity

Edge Sensitive

ETRIG

ANn_x

ETRIG

ASCIF

ANn_x

ETRIG

ASCIF

ANn_x

MAC7101 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

MAC7101 Datasheet(HTML) 28 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL