PAC7101 datasheet(18/56 Pages) FREESCALE

18 / 56 page

MAC7100 Microcontroller Family Hardware Specifications, Rev. 1.2

Preliminary

Electrical Characteristics

Freescale Semiconductor

3.8.3

PLL Characteristics

3.8.4

Crystal Monitor Time-out

The time-out Table 21 shows the delay for the crystal monitor to trigger when the clock stops, either at the high

or at the low level. The corresponding clock period with an ideal 50% duty cycle is twice this time-out value.

3.8.5

Clock Quality Checker

The timing for the clock quality check is derived from the oscillator and the VCO frequency range in

Table 20. These numbers define the upper time limit for the individual check windows to complete.

Table 20. PLL Characteristics

Num C

Rating

Symbol

Min

Typ

Max

Unit

PLL reference frequency, crystal oscillator range

fREF

0.5

—

MHz

P Self Clock Mode frequency

fSCM

2—

5.5

MHz

D VCO locking range

fVCO

NOTES:

1. If CLKSEL[PLLSEL] is set then the system clock (fSYS) is equal to fVCO, otherwise it is equal to fOSC (table Table 19,

J1a or J1b). Throughout this document, tSYS is used to specify a unit of time equal to 1 ÷ fSYS.

8—

MHz

D Lock Detector transition from Acquisition to Tracking mode

|Δ

trk|

3—4

% 2

2. Percentage deviation from target frequency

D Lock Detection

|Δ

Lock|

0—

1.5

% 2

D Un-Lock Detection

|Δ

unl|

0.5

—

2.5

% 2

D Lock Detector transition from Tracking to Acquisition mode

|Δ

unt|

6—8

% 2

C PLLON Total Stabilization delay (Auto Mode) 3

3. PLL stabilization delay is highly dependent on operational requirement and external component values (for

example, crystal and XFC filter component values). Notes 4 and 5 show component values for a typical

configurations. Appropriate XFC filter values should be chosen based on operational requirement of system.

tstab

—0.5 4

4. fOSC = 4 MHz, fVCO = 40 MHz (REFDV = 0x00, SYNR = 0x04), CS = 2.2 nF, CP = 220 pF, RS = 5.6 KΩ.

3 5

5. fOSC = 4 MHz, fVCO = 16 MHz (REFDV = 0x00, SYNR = 0x01), CS = 4.7 nF, CP = 470 pF, RS = 2.7 KΩ.

D PLLON Acquisition mode stabilization delay 3

tacq

—0.3 4

1 5

K10

D PLLON Tracking mode stabilization delay 3

tal

—0.2 4

2 5

K11

D Charge pump current acquisition mode

| i

ch |

—

38.5

—

μA

K12

D Charge pump current tracking mode

| i

ch |

—3.5

—

μA

K13

D Jitter fit VCO loop gain parameter

—

–195

—

MHz/V

K14

D Jitter fit VCO loop frequency parameter

—

126

—

MHz

K15

C Jitter fit parameter 1

——

1.3

% 4

K16

C Jitter fit parameter 2

—

0.12

% 4

Table 21. Crystal Monitor Time-Outs

Min

Typ

Max

Unit

610

18.5

μs

Table 22. CRG Maximum Clock Quality Check Timings

Clock Check Windows

Value

Unit

Check Window

9.1 to 20.0

Timeout Window

0.46 to 1.0

PAC7101 Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

PAC7101 Datasheet(HTML) 18 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Datasheet Download

Link URL