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TVP7002PZP Datasheet(PDF) 34 Page - Texas Instruments

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Part # TVP7002PZP
Description  TRIPLE 8-/10-BIT 165-/110-MSPS, VIDEO AND GRAPHICS DIGITIZER WITH HORIZONTAL PLL
PDF  52 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TVP7002PZP Datasheet(HTML) 34 Page - Texas Instruments

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MISC Control 2
MISC Control 3
TVP7002
SLES206 – MAY 2007
Subaddress
17h
Default (03h)
7
6
5
4
3
2
1
0
Reserved
Test output control [2:0]
Reserved
SOG En
Output En
Test output control [2:0]: Selects which signal is output on pin 22. Output polarity control is also provided using bit 2 of subaddress 18h.
000 = Field ID output (default)
001 = Data Enable output
010 = Reserved
011 = Reserved
100 = Internal clock reference output (~6.3 MHz typical)
101 = Coast output
110 = Clamp pulse output
111 = High-impedance mode
SOG En: Active low output enable for SOGOUT output.
0 = SOG output enabled
1 = SOG output placed in high-impedance mode (default)
Output En: Active low output enable for RGB, DATACLK, HSOUT, VSOUT, and FIDOUT outputs. This control bit allows selecting a
high-impedance output mode for multiplexing the output of the TVP7002 with another device.
0 = Outputs enabled
1 = Outputs placed in high-impedance mode (default)
Note: Data Enable output is equivalent to the internal active video signal that is controlled by the AVID start/stop pixel
values and the VBLK offset/duration line values.
Subaddress
18h
Default (00h)
7
6
5
4
3
2
1
0
Reserved
Reserved
Blank En
CSC En
Reserved
FID POL
SOG POL
CLK POL
Reserved [7]:
0 = Required (default)
Blank En: Active high blank level enable. Forces the video blank level to a standard value when using embedded syncs.
0 = Normal operation (default)
1 = Force standard blank levels
CSC En: Active high CSC enable. When disabled, the CSC block is bypassed.
0 = CSC disabled (default)
1 = CSC enabled
FID POL: Active high Field ID output polarity control. Under normal operation, the field ID output is set to logic 1 for an odd field (field 1) and
set to logic 0 for an even field (field 0).
0 = Normal operation (default)
1 = FID output polarity inverted
Note: This control bit also affects the polarity of the data enable output when selected (see Test output control [2:0] at
subaddress 17h).
SOG POL: Active high SOG output polarity control
0 = Normal operation (default)
1 = SOG output polarity inverted
CLK POL: Allows selecting the polarity of the output data clock.
0 = Data is clocked out on rising edge of DATACLK (default)
1 = Data is clocked out on falling edge of DATACLK
34
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