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TVP7002PZP Datasheet(PDF) 47 Page - Texas Instruments |
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TVP7002PZP Datasheet(HTML) 47 Page - Texas Instruments |
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47 / 52 page ![]() www.ti.com VBLK Field 0 Duration VBLK Field 1 Duration F-bit Field 0 Start Line Offset F-bit Field 1 Start Line Offset 1st CSC Coefficient 2nd CSC Coefficient 3rd CSC Coefficient TVP7002 SLES206 – MAY 2007 Subaddress 46h Default (1Eh) 7 6 5 4 3 2 1 0 VBLK duration 0 [7:0] VBLK duration 0 [7:0]: VBLK duration in lines for field 0. Subaddress 47h Default (1Eh) 7 6 5 4 3 2 1 0 VBLK duration 1 [7:0] VBLK duration 1 [7:0]: VBLK duration in lines for field 1. Subaddress 48h Default (00h) 7 6 5 4 3 2 1 0 F-bit start 0 [7:0] F-bit start 0 [7:0]: F-bit Field 0 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 0 until field 1 start line, it only applies in interlaced mode. For a non-interlace mode, F-bit is always set to 0. Note: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT). Subaddress 49h Default (00h) 7 6 5 4 3 2 1 0 F-bit start 1 [7:0] F-bit start 1 [7:0]: F-bit Field 1 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 1 until field 0 start line, it only applies in interlaced mode. For a non-interlace mode, F-Bit is always set to 0. Note: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT). Subaddress 4Ah–4Bh Default (16E3h) Subaddress 7 6 5 4 3 2 1 0 4Ah 1st Coefficient [7:0] 4Bh 1st Coefficient [15:8] 1st Coefficient [15:0]: 16-bit G’ coefficient MSB for Y Subaddress 4Ch–4Dh Default (024Fh) Subaddress 7 6 5 4 3 2 1 0 4Ch 2nd Coefficient [7:0] 4Dh 2nd Coefficient [15:8] 2nd Coefficient [15:0]: 16-bit B’ coefficient MSB for Y Subaddress 4Eh–4Fh Default (06CEh) Subaddress 7 6 5 4 3 2 1 0 4Eh 3rd Coefficient [7:0] 4Fh 3rd Coefficient [15:8] 3rd Coefficient [15:0]: 16-bit R’ coefficient MSB for Y 47 Submit Documentation Feedback |
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