LPD6803 datasheet

8

This mode (OMODE=high level voltage or dangle) is suitable in several LEDs and

VDD is higher than 12V, its essence is to higher capability of withstand

voltage in the

time of keeping characteristic of constant current in the circuit.

Current passed LED : ILED= Io*β/(β+1)

Here Io is current value related to chart 1, transistor is working in amplify

area,

Βis amplify multiple, whenβ is bigger, above formula can be near equal to :

Iled = Io (bias resistance RB can be get as 5k)

Highest capability of withstand voltage VDD is decided by VCEO on NPN

transistor, normally is 25V or above.

Linking signal driver and link:

Considering of that the distance between of chips may be long long, DOUT and

DCLKO

Output terminal is designed to push-pull strong drive circuit, after testing,

it can drive 6meters length signal line when clock is 2M, to prevent signal

echo, normally, pls serial a 50Ω resistance at DOUT and DCLKO, then output to

next step.

Control circuit and software reference design:

Via set CMODE, LPD6803 grey level counter can adapt DCLK as clock( CMODE=0),

Also can adapt built-in 1.2M(error ±15%)osscilator output of as clock(CMODE=1

Or dangle), prior one is normally used in those based on CPLD/FPGA high cost

control system, later one is often used in low cost MCU control system.

In CMODE=1 mode, MCU write display data into chip via SPI or two GPIO interface

line,

then each chip will automatically produce drive output with related duty cycle

according to input grey level value, after data transfered, MCU can deal with