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56F8335 Datasheet(PDF) 115 Page - Freescale Semiconductor, Inc |
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56F8335 Datasheet(HTML) 115 Page - Freescale Semiconductor, Inc |
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115 / 160 page  Power-Down Modes Overview 56F8335 Technical Data, Rev. 5 Freescale Semiconductor 115 Preliminary 6.7 Power-Down Modes Overview The 56F8335/56F8135 operate in one of three power-down modes, as shown in Table 6-3 . All peripherals, except the COP/watchdog timer, run off the IPBus clock frequency, which is the same as the main processor frequency in this architecture. The maximum frequency of operation is SYS_CLK = 60MHz. Table 6-3 Clock Operation in Power-Down Modes Mode Core Clocks Peripheral Clocks Description Run Active Active Device is fully functional Wait Core and memory clocks disabled Active Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. Stop System clocks continue to be generated in the SIM, but most are gated prior to reaching memory, core and peripherals. The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset |
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