56F8335 datasheet(114/160 Pages) FREESCALE

114 / 160 page

56F8335 Technical Data, Rev. 5

114

Freescale Semiconductor

Preliminary

registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register

to its previous contents prior to returning from interrupt.

Note:

The default value of this register set points to the EOnCE registers.

Note:

The pipeline delay between setting this register set and using short I/O addressing with the new value

is three cycles.

Figure 6-14 I/O Short Address Location High Register (SIM_ISALH)

6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0

This field represents the upper two address bits of the “hard coded” I/O short address.

Figure 6-15 I/O Short Address Location Low Register (SIM_ISAL)

6.5.10.2 Input/Output Short Address Low (ISAL[21:6])—Bit 15–0

This field represents the lower 16 address bits of the “hard coded” I/O short address.

6.6 Clock Generation Overview

The SIM uses an internal master clock from the OCCS (CLKGEN) module to produce the peripheral and

system (core and memory) clocks. The maximum master clock frequency is 120MHz. Peripheral and

system clocks are generated at half the master clock frequency and therefore at a maximum 60MHz. The

SIM provides power modes (Stop, Wait) and clock enables (SIM_PCE register, CLK_DIS, ONCE_EBL)

to control which clocks are in operation. The OCCS, power modes, and clock enables provide a flexible

means to manage power consumption.

Power utilization can be minimized in several ways. In the OCCS, crystal oscillator, and PLL may be shut

down when not in use. When the PLL is in use, its prescaler and postscaler can be used to limit PLL and

master clock frequency. Power modes permit system and/or peripheral clocks to be disabled when unused.

Clock enables provide the means to disable individual clocks. Some peripherals provide further controls

to disable unused subfunctions. Refer to Part 3 On-Chip Clock Synthesis (OCCS), and the 56F8300

Peripheral User Manual for further details.

Base + $D

Read

ISAL[23:22]

Write

RESET

11111

Base + $E

Read

ISAL[21:6]

Write

RESET

11111

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