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56F8335 Datasheet(PDF) 113 Page - Freescale Semiconductor, Inc |
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56F8335 Datasheet(HTML) 113 Page - Freescale Semiconductor, Inc |
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113 / 160 page ![]() Register Descriptions 56F8335 Technical Data, Rev. 5 Freescale Semiconductor 113 Preliminary • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.14 Serial Peripheral Interface 0 Enable (SPI0)—Bit 2 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.15 Pulse Width Modulator B Enable (PWMB)—Bit 1 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.16 Pulse Width Modulator A Enable (PWMA)—Bit 0 Each bit controls clocks to the indicated peripheral. • 1 = Clocks are enabled • 0 = The clock is not provided to the peripheral (the peripheral is disabled) 6.5.10 I/O Short Address Location Register (SIM_ISALH and SIM_ISALL) The I/O Short Address Location registers are used to specify the memory referenced via the I/O short address mode. The I/O short address mode allows the instruction to specify the lower six bits of address; the upper address bits are not directly controllable. This register set allows limited control of the full address, as shown in Figure 6-13. Note: If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. Figure 6-13 I/O Short Address Determination With this register set, an interrupt driver can set the SIM_ISALL register pair to point to its peripheral Instruction Portion “Hard Coded” Address Portion 16 Bits from SIM_ISALL Register 2 Bits from SIM_ISALH Register Full 24-Bit for Short I/O Address 6 Bits from I/O Short Address Mode Instruction |
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