56F8335 datasheet(110/160 Pages) FREESCALE

110 / 160 page

56F8335 Technical Data, Rev. 5

110

Freescale Semiconductor

Preliminary

Figure 6-11 GPIO Peripheral Select Register (SIM_GPS)

6.5.8.1

Reserved—Bits 15–4

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

6.5.8.2

GPIOC3 (C3)—Bit 3

This bit selects the alternate function for GPIOC3.

•

0 = HOME1/TB3 (default - see “Switch Matrix Mode” bits of the Quad Decoder DECCR register in the

56F8300 Peripheral User’s Manual)

•

1 = SS1

6.5.8.3

GPIOC2 (C2)—Bit 2

This bit selects the alternate function for GPIOC2.

•

0 = INDEX1/TB2 (default)

•1 = MISO1

6.5.8.4

GPIOC1 (C1)—Bit 1

This bit selects the alternate function for GPIOC1.

Quad Timer Input /

Quad Decoder

Input 2

—

See the “Switch Matrix for Inputs to the Timer”

table in the 56F8300 Peripheral User Manual

for the definition of timer inputs based on the

Quad Decoder mode configuration.

Quad Timer

Output / Quad

Decoder Input 3

1—

SPI input

—

See SPI controls for determining the direction

of each of the SPI pins.

SPI output

—

1. This applies to the four pins that serve as Quad Decoder / Quad Timer / SPI / GPIOC functions. A separate set of control

bits is used for each pin.

2. Reset configuration

3. Quad Decoder pins are always inputs and function in conjunction with the Quad Timer pins.

Base + $B

Read

Write

RESET

Table 6-2 Control of Pads Using SIM_GPS Control 1

Pin Function

Control Registers

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