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TUSB564 Datasheet(PDF) 11 Page - Texas Instruments |
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TUSB564 Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 54 page  5.7 Switching Characteristics (continued) over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TCTL1_DE BOUNCE CTL1 and HPDIN debounce time when transitioning from H to L 3 10 ms I2C (SDA and SCL) fSCL I2C clock frequency 1 MHz tBUF Bus free time between START and STOP conditions 0.5 µs tHDSTA Hold time after repeated START condition. After this period, the first clock pulse is generated 0.26 µs tLOW Low period of the I2C clock 0.5 µs tHIGH High period of the I2C clock 0.26 µs tSUSTA Setup time for a repeated START condition 0.26 µs tHDDAT Data hold time 0 µs tSUDAT Data setup time 50 ns tR Rise time of both SDA and SCL signals 120 ns tF Fall time of both SDA and SCL signals 20 × (VI2C/5.5 V) 120 ns tSUSTO Setup time for STOP condition 0.26 µs Cb Capacitive load for each bus line 100 pF www.ti.com TUSB564-Q1 SLLSFO9 – MAY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TUSB564-Q1 |
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