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PUMH7 Datasheet(PDF) 2 Page - NXP Semiconductors |
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PUMH7 Datasheet(HTML) 2 Page - NXP Semiconductors |
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2 / 8 page ![]() 1999 Apr 22 2 Philips Semiconductors Product specification NPN resistor-equipped double transistor PUMH7 FEATURES • Transistors with built-in bias resistor R1 (typ. 4.7 k Ω) • No mutual interference between the transistors • Simplification of circuit design • Reduces number of components and board space. APPLICATIONS • Especially suitable for space reduction in interface and driver circuits • Inverter circuit configurations without use of external resistors. DESCRIPTION NPN resistor-equipped double transistor in an SC-88 (SOT363) plastic package. PINNING PIN DESCRIPTION 1, 4 emitter TR1; TR2 2, 5 base TR1; TR2 6, 3 collector TR1; TR2 Fig.1 Simplified outline (SC-88; SOT363) and symbol. handbook, halfpage MAM380 65 4 12 3 TR1 TR2 R1 R1 13 2 4 5 6 Top view Fig.2 Equivalent inverter symbol. MBK120 2, 5 6, 3 1, 4 MARKING TYPE NUMBER MARKING CODE PUMH7 Ht7 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). Note 1. Refer to SC-88 standard mounting conditions. SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT Per transistor VCBO collector-base voltage open emitter − 50 V VCEO collector-emitter voltage open base − 50 V VEBO emitter-base voltage open collector − 5V IO output current (DC) − 100 mA ICM peak collector current − 100 mA Ptot total power dissipation Tamb ≤ 25 °C; note 1 − 200 mW Tstg storage temperature −65 +150 °C Tj junction temperature − 150 °C Tamb operating ambient temperature −65 +150 °C Per device Ptot total power dissipation Tamb ≤ 25 °C − 300 mW |
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