XRT84L38 datasheet(13/453 Pages) EXAR

13 / 453 page

XRT84L38

REV. 1.0.1

OCTAL T1/E1/J1 FRAMER

FIGURE 108. E1 TRANSMIT OVERHEAD INPUT INTERFACE TIMING ................................................................................................. 313

8.2 E1 RECEIVE OVERHEAD INTERFACE ......................................................................................................... 313

8.2.1 DESCRIPTION OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE BLOCK ............................................... 313

FIGURE 109. BLOCK DIAGRAM OF THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE OF XRT84L38 .............................................. 314

8.2.2 CONFIGURE THE E1 RECEIVE OVERHEAD OUTPUT INTERFACE MODULE AS SOURCE OF THE NATIONAL BIT

SEQUENCE IN E1 FRAMING FORMAT MODE.......................................................................................................... 314

RECEIVE SIGNALING AND DATA LINK SELECT REGISTER (RSDLSR) (INDIRECT ADDRESS = 0XN0H, 0X0CH) 314

FIGURE 110. E1 RECEIVE OVERHEAD OUTPUT INTERFACE TIMING................................................................................................ 315

9.0 DS1 TRANSMIT FRAMER BLOCK ..................................................................................................... 316

9.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN DS1 MODE ................................................................. 316

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H)................................................. 316

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H).............................................. 316

9.2 HOW TO CONFIGURE THE FRAMER TO TRANSMIT DATA IN VARIOUS DS1 FRAMING FORMATS .... 317

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H) .............................................. 317

9.2.1 HOW TO CONFIGURE THE FRAMER TO INPUT FRAMING ALIGNMENT BITS FROM DIFFERENT SOURCES 317

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) ................................... 318

9.2.2 HOW TO CONFIGURE THE FRAMER TO INPUT CRC-6 BITS FROM DIFFERENT SOURCES ............................ 318

SYNCHRONIZATION MUX REGISTER (SMR) (INDIRECT ADDRESS = 0XN0H, 0X09H) ................................... 319

9.3 HOW TO CONFIGURE THE FRAMER TO APPLY DATA AND SIGNALING CONDITIONING TO DS1 PAYLOAD

DATA ON A PER-CHANNEL BASIS............................................................................................................ 319

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) .......... 320

9.3.1 HOW TO APPLY USER IDLE CODE TO THE DS1 PAYLOAD DATA ...................................................................... 320

USER IDLE CODE REGISTER (UCR) (INDIRECT ADDRESS = 0XN02H, 0X20H - 0X37H) ............................ 321

9.4 HOW TO CONFIGURE THE XRT84L38 FRAMER TO APPLY ZERO CODE SUPPRESSION TO DS1 PAYLOAD

DATA ON A PER-CHANNEL BASIS............................................................................................................ 321

TRANSMIT CHANNEL CONTROL REGISTER (TCCR) (INDIRECT ADDRESS = 0XN2H, 0X00H - 0X1FH) ......... 321

9.5 HOW TO CONFIGURE THE XRT84L38 FRAMER TO TRANSMIT ROBBED-BIT SIGNALING INFORMATION

321

9.5.1 BRIEF DISCUSSION OF ROBBED-BIT SIGNALING IN DS1 FRAMING FORMAT ................................................. 322

9.5.2 CONFIGURE THE FRAMER TO TRANSMIT ROBBED-BIT SIGNALING................................................................. 323

9.5.2.1 INSERT SIGNALING BITS FROM TSCR REGISTER ................................................................................................. 323

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ........ 324

9.5.2.2 INSERT SIGNALING BITS FROM TXSIG_N PIN ....................................................................................................... 324

FIGURE 111. TIMING DIAGRAM OF THE TXSIG_N INPUT ................................................................................................................. 324

TRANSMIT INTERFACE CONTROL REGISTER (TICR) (INDIRECT ADDRESS = 0XN0H, 0X20H)........................ 325

9.5.2.3 INSERT SIGNALING DATA FROM TXSER_N PIN..................................................................................................... 325

9.5.2.4 ENABLE ROBBED-BIT SIGNALING AND SIGNALING DATA SOURCE CONTROL ........................................................ 325

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ........ 325

TRANSMIT SIGNALING CONTROL REGISTER (TSCR) (INDIRECT ADDRESS = 0XN2H, 0X40H - 0X57H) ........ 326

9.6 HOW TO CONFIGURE THE XRT84L38 FRAMER TO GENERATE AND TRANSMIT ALARMS AND ERROR IN-

DICATIONS TO REMOTE TERMINAL ......................................................................................................... 326

9.6.1 BRIEF DISCUSSION OF ALARMS AND ERROR CONDITIONS .............................................................................. 326

FIGURE 112. SIMPLE DIAGRAM OF DS1 SYSTEM MODEL .............................................................................................................. 327

FIGURE 113. GENERATION OF YELLOW ALARM BY THE CPE UPON DETECTION OF LINE FAILURE..................................................... 328

FIGURE 114. GENERATION OF AIS BY THE REPEATER UPON DETECTION OF YELLOW ALARM ORIGINATED BY THE CPE................... 329

FIGURE 115. GENERATION OF YELLOW ALARM BY THE CPE UPON DETECTION OF AIS ORIGINATED BY THE REPEATER ................... 330

9.6.2 HOW TO CONFIGURE THE FRAMER TO TRANSMIT AIS ...................................................................................... 330

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H).......................................... 331

9.6.3 HOW TO CONFIGURE THE FRAMER TO GENERATE RED ALARM ..................................................................... 331

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H).......................................... 331

9.6.4 HOW TO CONFIGURE THE FRAMER TO TRANSMIT YELLOW ALARM ............................................................... 331

9.6.4.1 TRANSMIT YELLOW ALARM IN SF MODE ............................................................................................................. 331

9.6.4.2 TRANSMIT YELLOW ALARM IN ESF MODE........................................................................................................... 332

9.6.4.3 TRANSMIT YELLOW ALARM IN N MODE ............................................................................................................... 332

9.6.4.4 TRANSMIT YELLOW ALARM IN T1DM MODE ........................................................................................................ 332

ALARM GENERATION REGISTER (AGR) (INDIRECT ADDRESS = 0XN0H, 0X08H).......................................... 333

10.0 DS1 RECEIVE FRAMER BLOCK...................................................................................................... 334

10.1 HOW TO CONFIGURE XRT84L38 TO OPERATE IN DS1 MODE ............................................................... 334

CLOCK SELECT REGISTER (CSR) (INDIRECT ADDRESS = 0XN0H, 0X00H)................................................. 334

FRAMING SELECT REGISTER (FSR) (INDIRECT ADDRESS = 0XN0H, 0X07H).............................................. 334

10.2 HOW TO CONFIGURE THE FRAMER TO RECEIVE DATA IN VARIOUS DS1 FRAMING FORMATS ..... 335

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