XRT86VL32 datasheet(27/65 Pages) EXAR

27 / 65 page

XRT86VL32

REV. V1.2.0

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

RxCHN0_3/

Rx8KHZ0

RxCHN2_3/

Rx8KHZ2

C10

L16

Receive Time Slot Octet Identifier Output-Bit 3 (RxCHNn_3)

/ Receive 8KHz Clock Output (Rx8KHZn):

The exact function of these pins depends on whether or not the

receive framer enables the receive fractional/signaling inter-

face, as described below:

If receive fractional/signaling interface is disabled -

RxCHNn_3:

These output pins (RxCHNn_4 through RxCHNn_0) reflect the

five-bit binary value of the current time slot being output by the

receive serial interface. System equipment can use the RxCH-

CLKn to sample the five output pins of each channel to identify

the time slot being output on these pins. RxCHNn_3 indicates

Bit 3 of the time slot channel being output.

If receive fractional/signaling interface is enabled -

Rx8KHZn:

These pins output a reference 8KHz clock signal derived from

the MCLKIN input.

NOTE: Receive Fractional/Signaling interface can be enabled

by programming to bit 4 - RxFr1544/RxFr2048 bit from

RxCHN0_4/

RxSCLK0

RxCHN2_4/

RxSCLK2

B10

K16

Receive Time Slot Octet Identifier Output-Bit 4 (RxCHNn_4)

/ Receive Recovered Line Clock Output (RxSCLKn):

The exact function of these pins depends on whether or not the

receive framer enables the receive fractional/signaling inter-

face, as described below:

If receive fractional/signaling interface is disabled -

RxCHNn_4:

These output pins (RxCHNn_4 through RxCHNn_0) reflect the

five-bit binary value of the current time slot being output by the

receive serial interface. System equipment can use the RxCH-

CLKn to sample the five output pins of each channel to identify

the time slot being output on these pins. RxCHNn_4 indicates

the Most Significant Bit (MSB) of the time slot channel being

output.

If receive fractional/signaling interface is enabled - Receive

Recovered Line Clock Output (RxSCLKn):

These pins output the recovered T1/E1 line clock (1.544MHz in

T1 mode and 2.048MHz in E1 mode) for each channel.

NOTE: Receive Fractional/Signaling interface can be enabled

by programming to bit 4 - RxFr1544/RxFr2048 bit from

RECEIVE SYSTEM SIDE INTERFACE

SIGNAL NAME

BALL #TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

XRT86VL32 Datasheet(PDF) 27 Page - Exar Corporation

XRT86VL32 Datasheet(HTML) 27 Page - Exar Corporation

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