XRT86VL32 datasheet(34/65 Pages) EXAR

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XRT86VL32

DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION

REV. V1.2.0

MICROPROCESSOR INTERFACE

SIGNAL NAME

BALL #

TYPE

OUTPUT

DRIVE (MA)

DESCRIPTION

DATA0

DATA1

DATA2

DATA3

DATA4

DATA5

DATA6

DATA7

T10

V10

U11

R11

I/O

Bidirectional Microprocessor Data Bus

These pins are used to drive and receive data over the bi-direc-

tional data bus, whenever the Microprocessor performs READ

or WRITE operations with the Microprocessor Interface of the

XRT86VL32 device.

When DMA interface is enabled, these 8-bit bidirectional data

bus is also used by the T1/E1 Framer or the external DMA

Controller for storing and retrieving information.

REQ0

DMA Cycle Request Output—DMA Controller 0 (Write):

These output pins are used to indicate that DMA transfers

(Write) are requested by the T1/E1 Framer.

On the transmit side (i.e., To transmit data from external DMA

controller to HDLC buffers within the XRT86VL32), DMA trans-

fers are only requested when the transmit buffer status bits

indicate that there is space for a complete message or cell.

The DMA Write cycle starts by T1/E1 Framer asserting the

DMA Request (REQ0) ‘low’, then the external DMA controller

should drive the DMA Acknowledge (ACK0) ‘low’ to indicate

that it is ready to start the transfer. The external DMA controller

should place new data on the Microprocessor data bus each

time the Write Signal is Strobed low if the WR is configured as

a Write Strobe. If WR is configured as a direction signal, then

the external DMA controller would place new data on the

Microprocessor data bus each time the Read Signal (RD) is

Strobed low.

The Framer asserts this output pin (toggles it "Low") when at

least one of the Transmit HDLC buffers are empty and can

receive one more HDLC message.

The Framer negates this output pin (toggles it “High”) when the

HDLC buffer can no longer receive another HDLC message.

XRT86VL32 Datasheet(PDF) 34 Page - Exar Corporation

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