XRT94L33 datasheet(73/810 Pages) EXAR

73 / 810 page

XRT94L33

Rev 2

22 ...0

00 ...0

33 ---C

C H

H A

A N

N N

N E

E L

L D

D S

S 3

33 ///E

E 3

33 ///S

S T

T S

S -

-- 1

11 T

T O

O S

S T

T S

S -

-- 3

33 ///S

S T

T M

M -

-- 1

11 M

M A

A P

P P

P E

E R

R –

–– S

S D

D H

H R

R E

E G

G IIIS

S T

T E

E R

R S

“STS1TXA_C1J1_0” and STS1RXD_C1J1_0” signals, as described below.

0 – C1 and J1 Bytes

This selection configures the following.

The

STM-0

Receive

Telecom

Bus

pulse

the

“STS1RXD_C1J1_0” output coincident to whenever the C1 and J1

bytes are being output via the “STS1RXD_D_0[7:0]” output pins.

The

STM-0

Transmit

Telecom

Bus

will

expect

the

“STS1TXA_C1J1_0” input to pulse “high” coincident to whenever

the

and

bytes

are

being

sampled

via

the

“STS1TXA_D_0[7:0]” input pins.

1 – J1 Bytes Only

This selection configures the following.

The STM-0 Receive Telecom Bus Interface to only pulse the

“STS1RXD_C1J1_0” output pin coincident to whenever the J1 byte

is being output via the “STS1RXD_D_0[7:0]” output pins.

Note:

The “STS1RXD_C1J1_0” output pin will NOT be pulsed “high”

whenever

the

byte

being

output

via

the

“STS1RXD_D_0[7:0]” output pins

The STM-0 Transmit Telecom Bus Interface will expect the

“STS1TXA_C1J1_0” input to only pulse “high” coincident to

whenever

the

byte

being

sampled

via

the

“STS1TXA_D_0[7:0]” input pins.

Note:

The “STS1TXA_C1J1_0” input pin will NOT be pulsed “high”

whenever the C1 byte is being input via the “STS1TXA_D_0[7:0]”

input pins

Bit 2

STM-0

Telecom Bus

Parity Odd

R/W

Telecom Bus Parity – ODD Parity Select – Channel 0:

This READ/WRITE bit-field permits the user to configure the

STM-0

Telecom Bus Interface, associated with Channel 0 to do the following.

In the Receive (Drop) Direction

Receive STM-0 Telecom Bus to compute either the EVEN or ODD parity

over the contents of the (1) STS1RxD_D_0[7:0] output pins, or (2)

STS1RxD_D_0[7:0] output pins, the states of the STS1RxD_PL_0 and

“STS1RxD_C1J1_0 output pins (depending upon user setting for Bit 3).

In the Transmit (Add) Direction

Transmit STM-0 Telecom Bus to compute and verify the EVEN or ODD

parity over the contents of the (1) STS1TxA_D_0[7:0] input pins, or (2)

STS1TxA_D_0[7:0] input pins, the states of the STS1TxA_PL_0 and

STS1TxA_C1J1_0 input pins (depending upon user setting for Bit 3).

0 – Configures Receive (Drop) Telecom Bus to compute EVEN parity and

configures the Transmit (Add) Telecom Bus to verify EVEN parity

1 – Configures Receive (Drop) Telecom Bus to compute ODD parity and

configures the Transmit (Add) Telecom Bus to verify ODD parity.

Bit 1

STM-0

Telecom Bus

Parity Disable

R/W

STM-0 Telecom Bus Parity Disable – Channel 0:

This READ/WRITE bit-field permits the user to either enable or disable

parity calculation and placement via the “STSRxD_DP_0” output pin.

Further, this bit field also permits the user to enable or disable parity

verification via the “STS1TxA_DP_0” input pin by the Transmit Telecom

Bus.

1 – Disables Parity Calculation (on the Receive Telecom Bus) and Disables

Parity Verification (on the Transmit Telecom Bus.

XRT94L33 Datasheet(PDF) 73 Page - Exar Corporation

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