SA7025 datasheet(13/22 Pages) PHILIPS

13 / 22 page

Philips Semiconductors

Product specification

SA7025

1GHz low-voltage Fractional-N synthesizer

1996 Aug 6

Table 3. PR Modulus

Modulus Prescaler

Bit Capacity

NM1

NM2

NM3

–

When the serial input A word is loaded, the output circuits are in the

“speed-up mode” as long as the STROBE is H, else the “normal

mode” is active. In the “normal mode” the current output PHP is:

PHP_N + IPHP ) IPHP_comp

where:

PHP| +

@ I

:charge pump current

PHP_comp| + FRD @

128

:fractional comp.

current

The current in PHI is zero in “normal mode”.

In “speed-up mode” the current in output PHP is:

PHP_S + IPHP ) IPHP_comp

PHP| +

@ I

(2CL)1

) 1)

PHP_comp| +

FRD

@ I

128

(2CL)1

) 1)

In “speed-up mode” the current in output PHI is:

PHI_S + IPHI ) IPHI_comp

where:

PHI| +

RNCN

(2CL)1)CK

PHI_comp| +

RF FRD

128

(2CL)1)CK

Figure 9 shows that for proper fractional compensation, the area of

the fractional compensation current pulse must be equal to the area

of the charge pump ripple output. This means that the current

setting on the input RN, RF is approximately:

@ f

VCO)

@ CN @ F

INR)

where:

fractional-N modulus

fVCO = fINM × N,

input frequency of the prescaler

FINR =

input frequency of the reference divider

PHI pump is meant for switching only. Current and compensation

are not as accurate as PHP.

REF_IN

REFERENCE

DIVIDER

AUX/MAIN

DIVIDER

“1”

N-TYPE

CHARGE PUMP

P-TYPE

CHARGE PUMP

VDDA

VSSA

REF_IN

SR00607

Figure 8. Phase Detector Structure with Timing

SA7025 Datasheet(PDF) 13 Page - NXP Semiconductors

SA7025 Datasheet(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL