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XRD9825 Datasheet(PDF) 21 Page - Exar Corporation |
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XRD9825 Datasheet(HTML) 21 Page - Exar Corporation |
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21 / 33 page ![]() XRD9825 21 Rev. 1.00 tdv tdv AREA, LINEAR or B/W CCD -- AC Coupled (CLAMP Enabled) Pixel N-1 Pixel N Pixel N+1 CCD Channel N ADCCLK tckpd tap tap tckhw tcklw CLAMP tclpw N-8 MSB N-8 LSB N-7 MSB N-7 LSB N-6 MSB N-6 LSB [5:0] [11:6] DB Figure 15. Timing Diagram for Figure 14 Triple Channel CCD Application Figure 6 is a block diagram for pixel-by-pixel applica- tions with triple channel CCDs. During the optically shielded section of a pixel, CLAMP must go high to store the black reference on each capacitor to the input. The gain and offset is automatically rotated to adjust for each channel input. The MSBs (8 upper bits) are available on the output bus on the falling edge of ADCCLK. The LSBs (8 lower bits) are available on the rising edge of ADCCLK. Note: There is an 8 clock latency at the output. |
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