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XR19L402 Datasheet(PDF) 21 Page - Exar Corporation |
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XR19L402 Datasheet(HTML) 21 Page - Exar Corporation |
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21 / 50 page  XR19L402 21 REV. 1.0.0 TWO CHANNEL INTEGRATED UART AND RS-485 TRANSCEIVER 3.0 UART INTERNAL REGISTERS The L402 has a set of configuration registers selected by address lines A0, A1 and A2 with CS# asserted. The complete register set is shown on Table 7 and Table 8. TABLE 7: UART INTERNAL REGISTERS ADDRESSES REGISTER READ/WRITE COMMENTS 16C550 COMPATIBLE REGISTERS 0 0 0 RHR - Receive Holding Register THR - Transmit Holding Register Read-only Write-only LCR[7] = 0 0 0 0 DLL - Divisor LSB Read/Write LCR[7] = 1, LCR ≠ 0xBF 0 0 1 DLM - Divisor MSB Read/Write 0 1 0 DLD - Divisor Fractional Read/Write LCR[7] = 1, LCR ≠ 0xBF, EFR[4] = 1 0 0 0 DREV - Device Revision Code Read-only DLL, DLM = 0x00, LCR[7] = 1, LCR ≠ 0xBF 0 0 1 DVID - Device Identification Code Read-only 0 0 1 IER - Interrupt Enable Register Read/Write LCR[7] = 0 0 1 0 ISR - Interrupt Status Register FCR - FIFO Control Register Read-only Write-only LCR ≠ 0xBF 0 1 1 LCR - Line Control Register Read/Write 1 0 0 MCR - Modem Control Register Read/Write LCR ≠ 0xBF 1 0 1 LSR - Line Status Register Read-only 1 1 0 MSR - Modem Status Register Read-only 1 1 1 SPR - Scratch Pad Register Read/Write LCR ≠ 0xBF, FCTR[6] = 0 1 1 1 FLVL - RX/TX FIFO Level Counter Register Read-only LCR ≠ 0xBF, FCTR[6] = 1 1 1 1 EMSR - Enhanced Mode Select Register Write-only ENHANCED REGISTERS 0 0 0 TRG - RX/TX FIFO Trigger Level Register FC - RX/TX FIFO Level Counter Register Write-only Read-only LCR = 0xBF 0 0 1 FCTR - Feature Control Register Read/Write 0 1 0 EFR - Enhanced Function Register Read/Write 1 0 0 Xon-1 - Xon Character 1 Read/Write 1 0 1 Xon-2 - Xon Character 2 Read/Write 1 1 0 Xoff-1 - Xoff Character 1 Read/Write 1 1 1 Xoff-2 - Xoff Character 2 Read/Write A2 A1 A0 |
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