XR68C192IV datasheet(11/33 Pages) EXAR

11 / 33 page

XR68C92/192

Rev. 1.33

or the FIFO-full status bits can be selected to cause an

interrupt (see MR1A, MR1B bit-6).

In addition to the data byte, three status bits (parity

error, framing error, and received break) are appended

to each data character in the FIFO (overrun is not). By

programming the error-mode control bit (MR1A, MR1B

bit-5), status can be provided for “character” or “block”

modes. In the “character” mode, the status register

(SRA, SRB) is updated on a character-by-character

basis and applies only to the character at the top of the

FIFO. Thus, the status must be read before the char-

acter is read. Reading the character pops the data byte

and its error flags off the FIFO. In the “block” mode, the

status provided in the status register for the parity error,

framing error, and received-break conditions are the

logical OR of these respective bits, for all the data bytes

in the FIFO stack since the last reset error command

(see CRA, CRB bits 7:4) was issued. That is, beginning

immediately after the last reset-error command was

issued, a continuous logical-OR function of corre-

sponding status bits is produced in the status register

as each character enters the FIFO.

The block mode is useful in applications requiring the

exchange of blocks of information where the software

overhead of checking each character's error flags

cannot be tolerated. In this mode, entire messages can

be received and only one data integrity check is per-

formed at the end of each message. Although data

reception in this manner has speed advantages, there

are also disadvantages. If an error occurs within a

message the error will not be recognized until the final

check is performed. Also, there is no indication of

which character(s) is in error within the message.

Reading the status register (SRA, SRB) does not affect

the FIFO. The FIFO is “popped” only when the receive

buffer is read. If the FIFO is full when a new character

is received, that character is held in the receive shift

tional character is received while this state exists, the

contents of the FIFO are not affected, but the character

previously in the shift register is lost and the overrun-

error status bit will be set upon receipt of the start bit of

the new overrunning character.

To support flow control, a receiver can automatically

negate and reassert the request-to-send (RTS) output

(RX RTS control - see MR1A, MR1B bit-7). The re-

quest-to-send output (at OP0 or OP1 for channel A or

B respectively) will automatically be negated by the

receiver when a valid start bit is received and the FIFO

stack is full. When a FIFO position becomes available,

the request-to-send output will be reasserted auto-

matically by the receiver. Connecting the request-to-

send output to the clear-to send (CTS) input of a

transmitting device prevents overrun errors in the

receiver. The RTS output must be manually asserted

the first time. Thereafter, the receiver will control the

RTS output.

If the FIFO stack contains characters and the receiver

is then disabled, the characters in the stack can still be

read but no additional characters can be received until

the receiver is again enabled. If the receiver is disabled

while receiving a character, or while there is a charac-

ter in the shift register waiting for a FIFO opening, these

characters are lost. If the receiver is reset, the FIFO

stack and all of the receiver status bits, the correspond-

ing output ports, and the interrupt request are reset. No

additional characters can be received until the receiver

is again enabled.

LOOPBACK MODES

Besides the normal operation mode in which the re-

ceiver and transmitter operate independently, each

XR68C92/192 channel can be configured to operate in

various looping modes (see MR2A, MR2B bits 7:6) that

are useful for local and remote system diagnostic

functions.

AUTOMATIC ECHO MODE

In this mode, the channel automatically retransmits the

received data on a bit-by-bit basis. The local CPU-to-

receiver communication continues normally but the

CPU-to-transmitter link is disabled.

LOCAL LOOPBACK MODE

In this mode, the transmitter output is internally con-

nected to the receiver input. The external TX pin is held

in the mark (high) state in this mode. By sending data

to the transmitter and checking that the data as-

sembled by the receiver is the same data that was sent,

proper channel operation can be assured. In this mode

the CPU-to-transmitter and CPU-to-receiver commu-

nications continue normally.

REMOTE LOOPBACK MODE

In this mode, the channel automatically retransmits the

received data on a bit-by-bit basis. The local CPU-to-

receiver and CPU-to-transmitter links are disabled.

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