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SP6125 Datasheet(PDF) 8 Page - Sipex Corporation |
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SP6125 Datasheet(HTML) 8 Page - Sipex Corporation |
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8 / 12 page  Mar22-07 RevC SP6125: TSOT-6 PFET Buck Controller 2007 Sipex Corporation 8 This causes an overshoot in output voltage that is corrected by power switch reduced duty cycle. Use the following equation to calculate COUT: − × = 2 2 Vout - Vos 1 2 I I L Cout Where: L is the output inductance I 2 is the step load high current I 1 is the step load low current Vos is output voltage including overshoot VOUT is steady state output voltage Output voltage undershoot calculation is more complicated. Test results for SP6125 buck circuits show that undershoot is approximately equal to overshoot. Therefore above equation provides a satisfactory method for calculating COUT. Select ESR such that output voltage ripple (VRIP) specification is met. There are two components to VRIP: First component arises from charge transferred to and from COUT during each cycle. The second component of VRIP is due to inductor ripple current flowing through output capacitor’s ESR. It can be calculated from: 2 2 8 1 × × + × = fs Cout ESR Irip Vrip Where: IRIP is inductor ripple current fs is switching frequency COUT is output capacitor calculated above Note that a smaller inductor results in a higher IRIP , therefore requiring a larger COUT and/or lower ESR in order to meet VRIP. Input Capacitor Selection Select the input capacitor for Voltage, Capacitance, ripple current, ESR and ESL. Voltage rating is nominally selected to be twice the input voltage. The RMS value of input capacitor current, assuming a low inductor ripple current (Irip), can be calculated from: ( ) D D Iout Icin − × = 1 In general total input voltage ripple should be kept below 1.5% of VIN (not to exceed 180mV). Input voltage ripple has three components: ESR and ESL cause a step voltage drop upon turn on of the MOSFET. During on time capacitor discharges linearly as it supplies IOUT - IIN. The contribution to Input voltage ripple by each term can be calculated from: ( ) 2 , Vin Cin fs Vout Vin Vout Iout Cin V × × − × × = ∆ ( ) Irip Iout ESR ESR V 5 . 0 , − = ∆ ( ) Trise Irip Iout ESL ESL V 5 . 0 , − = ∆ Where Trise is the rise time of current through capacitor Total input voltage ripple is sum of the above: ESL V ESR V Cin V Tot V , , , , ∆ + ∆ + ∆ = ∆ In circuits where converter input voltage is applied via a mechanical switch excessive ringing may be present at turn-on that may interfere with smooth startup of SP6126. Addition of an inexpensive 100µF Aluminum Electrolytic capacitor at the input will help reduce ringing and restore a smooth startup. General Overview |
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