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SP6138 Datasheet(PDF) 10 Page - Sipex Corporation |
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SP6138 Datasheet(HTML) 10 Page - Sipex Corporation |
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10 / 17 page  0 Oct 24-06 Rev J SP638 Synchronous Buck Controller © 2006 Sipex Corporation LpisduetowiringandPCBtracesconnecting input capacitors and switching MOSFETs. For typical Lp of 2nH and Vin of 2V, di/dt is 1A/ns. Substituting for di/dt in equation (6) we get Qgd = 2 nC. In selecting a package type, the main con- siderations are cost, power/current handling capability and space constraints. A larger package in general offers higher power and current handling at increased cost. Package selection can be narrowed down by calculat- ing the required junction-to-ambient thermal resistance θja: θja = {Tj(max) - Ta(max)} / P(max)........... (7) Where: Tj(max) is the die maximum tem- perature rating, Ta(max) is maximum ambient temperature, and P(max) is maximum power dissipated in the die. It is common practice to add a guard-band of 25˚C to the junction temperature rating. Following this convention, a 150˚C rated MOSFETwillbedesignedtooperateat125˚C (i.e., Tj(max) = 125˚C). P(max) = 0.88W (from section 4) and Ta(max) = 40˚C as specified in the design example. Substituting in equation (7) we get θja = 96.6 ˚C/W. For the top MOSFET, we now have deter- mined the following requirements; BVdss = 30V, Rds(on) = 0.7mΩ, Qgd = 2 nC and θja < 96.6˚C/W.An SO-8 MOSFET that meets the requirements is Vishay-Siliconix’s Si4394DY; BVdss = 30V, Rds(on) = 9.75mΩ @ Vgs = 4.5V, Qgd = 2.nC and θja = 90 ˚C/W. The bottom MOSFET has the requirements of BVdss = 30V and Rds(on) = 5.4mΩ. Vishay- Siliconix’s Si4320DYmeets the requirements; BVdss = 30V, Rds(on) = 4mΩ @ Vgs = 4.5V. Power Good Power Good (PWRGD) is an open drain output that is pulled low when Vout is out- side regulation. The PWRGD pin can be connected to VCC with an external 0KΩ resistor. During startup, output regulates whenSoftStart(SS)reaches0.8V(therefer- ence voltage). PWRGD is enabled when SS reaches .6V. PWRGD output can be used as a “Power on Reset”. The simplest way to adjust delay of the “Power on Reset” signal with respect to Vout in regulation is with the Soft Start Capacitor (Css) and is given by: Css = (Iss x Tdelay)/0.8 where Iss is the Soft Start charge current (0µA nominal). Under Voltage Lock Out (UVLO) The SP638 has two separate UVLO com- parators to monitor the bias (Vcc) and Input (Vin)voltagesindependently.TheVccUVLO is internally set to 4.25V. The Vin UVLO is programmable through UVin pin. When UVIN pin is greater than 2.5V the SP638 is permitted to start up pending the removal of all other faults. A pair of internal resistors is connected to UVIN as shown in figure 4. Therefore without external biasing the Vin start threshold is 9.5V.Asmall capacitor may be required between UVIN and GND to filter out noise. For applications with Vin of 5V or 3.3V, connect UVIN directly to Vin. Figure 4- Internal and external bias of UVIN SP613X R4 R5 + - 40K 50K 2.5V ON 2.2V OFF GND UVIN VIN APPLICATION INFORMATION |
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