SP6138 datasheet(6/17 Pages) SIPEX

6 / 17 page

Oct 24-06 Rev J

SP638 Synchronous Buck Controller

THEORY OF OPERATION

The SP6138 contains two unique control

features that are very powerful in distributed

applications. First, non-synchronous driver

control is enabled during start up to prohibit

the low side NFETfrom pulling down the out-

put until the high side NFEThas attempted to

turn on. Second, a 00% duty cycle timeout

ensuresthatthelowsideNFETisperiodically

enhanced during extended periods at 00%

dutycycle.Thisguaranteesthesynchronized

refreshing of the BST capacitor during very

large duty ratios.

The SP638 also contains a number of valu-

able protection features. A programmable

input UVLO allows a user to set the exact

value at which the conversion voltage is at a

safe point to begin down conversion, and an

internalVCCUVLOensuresthatthecontroller

itselfhasenoughvoltagetoproperlyoperate.

Other protection features include thermal

shutdown and short-circuit detection. In the

event that either a

thermal, short-circuit, or UVLO fault is de-

tected,theSP638isforcedintoanidlestate

where the output drivers are held off for a

finite period before a re-start is attempted.

Soft Start

“Soft Start” is achieved when a power con-

verter ramps up the output voltage while

controlling the magnitude of the input sup-

ply source current. In a modern step down

converter,rampingupthenon-invertinginput

of the error amplifier controls soft start. As a

result, excess source current can be defined

as the current required to charge the output

capacitor

IVIN, X =

Cout • ∆Vout

∆TSoft-start

The SP638 provides the user with the op-

tion to program the soft start rate by tying

a capacitor from the SS pin to GND. The

selection of this capacitor is based on the

0µA pull up current present at the SS pin

and the 0.8V reference voltage. Therefore,

the excess current source can be redefined as:

IVIN, X = COUT • ∆VOUT •

0µA

(CSS • 0.8V)

Hiccup

Upon the detection of a power, thermal, or

short-circuit fault, the SP638 is forced into

an idle state for a minimum of 30ms. The SS

and COMP pins are immediately pulled low,

and the gate drivers are held off for the dura-

tionofthetimeoutperiod.Powerandthermal

faults have to be removed before a restart

may be attempted, whereas, a short-circuit

faultisinternallyclearedshortlyafterthefault

latch is set. Therefore, a restart attempt is

guaranteed every 30ms (typical) as long as

the short-circuit condition persists.

A short-circuit detection comparator has

also been included in the SP638 to protect

against the accidental short or severe build

up of current at the output of the power con-

verter. This comparator constantly monitors

the inputs to theerror amplifier, and if the

VFB pin ever falls more than 250mV (typical)

below the reference voltage, a short-circuit

fault is set. Because the SS pin overrides the

internal 0.8V reference during soft start, the

SP638 is capable of detecting short-circuit

faults throughout the duration of soft start as

well as in regular operation.

Error Amplifier & Voltage Loop

As stated before, the heart of the SP638

voltage error loop is a high performance,

wide bandwidth transconductance ampli-

fier. Because of the amplifier’s current

limited (+00µA) transconductance, there

are many ways to compensate the voltage

loop or to control the COMP pin externally.

If a simple, single pole, single zero response

is required, then compensation can be as

simple as an RC circuit to ground. If a more

complex compensation is required, then the

amplifierhasenoughbandwidthtorunTypeIII

compensation schemes with adequate gain

andphasemarginsatcrossoverfrequencies

greater than 200 kHz.

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