1995 Nov 03

10

Philips Semiconductors

Preliminary specification

YUV-to-RGB Digital-to-Analog

Converter (DAC)

SAA7167

AC CHARACTERISTICS

Notes

1. Switching time measured from the 50% point of the EXTKEY transition edge to the 50% point of the selected analog

output transition.

2. DAC output rise/fall time measured between the 10% and 90% points of full scale transition.

3. DAC settling time measured from the 50% point of full-scale transition to the output remaining within

±1 LSB.

4. DAC analog output propagation delay measured from the 50% point of the rising edge of VCLK to the 50% point of

full-scale transition.

SYMBOL

PARAMETER

MIN.

TYP.

MAX.

UNIT

video clock rate

−−

50

MHz

δ

duty factor of VCLK

−

50

−

%

PCLK

pixel clock rate (8-bit pixel colour key); see Fig.4

−−

50

MHz

pixel clock rate (2

× 8-bit pixel colour key; mode 1);

see Fig.5

−−

40

MHz

pixel clock rate (2

× 8-bit pixel colour key; mode 2);

see Fig.6

−−

80

MHz

pixel clock rate (3

× 8-bit pixel colour key); see Fig.7

−−

75

MHz

duty factor of PCLK

40

50

60

%

digital input set-up time to VCLK rising edge

3

−−

ns

digital input hold time to VCLK rising edge

3

−−

ns

digital input set-up time to PCLK rising edge

3

−−

ns

digital input hold time to PCLK rising edge

3

−−

ns

digital input set-up time to PCLK falling edge

3

−−

ns

digital input hold time to PCLK falling edge

3

−−

ns

switching time between video DAC/analog inputs;

note 1

−−

15

ns

overall group delay from digital video inputs to analog

outputs (see Fig.8):

YUV video input mode

−

−

ns

RGB video input mode

−

−

ns

DAC analog output rise time (see Fig.8); note 2

−

5

−

ns

DAC analog output fall time (see Fig.8); note 2

−

5

−

ns

DAC analog output settling time (see Fig.8); note 3

−−

15

ns

DAC analog output propagation delay (see Fig.8);

note 4

−

15

−

ns

Analog outputs from analog inputs

voltage gain

−

2.0

−

B

bandwidth (

−3 dB)

−

75

−

MHz

SR

slew rate

−

90

−

V/

µs