| Electronic Components Datasheet Search |
|
DS1990A Datasheet(PDF) 4 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
DS1990A Datasheet(HTML) 4 Page - Analog Devices |
|
4 / 10 page ![]() 64-Bit Unique ROM Each DS1990A contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a CRC of the first 56 bits. See Figure 2 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 3. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire Cyclic Redundancy Check (CRC) is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton Products. The shift register bits are initialized to 0. Then starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the 48th bit of the serial number has been entered, the shift register con- tains the CRC value. Shifting in the 8 bits of CRC returns the shift register to all 0s. 1-Wire Bus System The 1-Wire bus is a system that has a single bus master and one or more slaves. In all instances, the DS1990A is a slave device. The bus master is typically a micro- controller or PC. For small configurations, the 1-Wire communication signals can be generated under software control using a single port pin. Alternatively, the DS2480B 1-Wire line driver chip or serial-port adapters based on this chip (DS9097U series) can be used. This simplifies the hardware design and frees the microprocessor from responding in real time. The discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-Wire signaling (signal types and timing). The 1-Wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. For a more detailed protocol description, refer to Chapter 4 of the Book of iButton Standards. Figure 2. 64-Bit Unique ROM Figure 3. 1-Wire CRC Generator www.analog.com Analog Devices │ 4 DS1990A Serial Number iButton MSB 8-BIT CRC CODE 48-BIT SERIAL NUMBER MSB MSB LSB LSB LSB 8-BIT FAMILY CODE (01h) MSB LSB 1ST STAGE 2ND STAGE 3RD STAGE 4TH STAGE 7TH STAGE 8TH STAGE 6TH STAGE 5TH STAGE X0 X1 X2 X3 X4 POLYNOMIAL = X8 + X5 + X4 + 1 INPUT DATA X5 X6 X7 X8 |
|
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |