Clock pulse high duration

50

ns

Integration time

Tint(1)

0.270

5.0

ms

Operating temperature

Top

25

50

Note: Minimum Tint is measured with the longest array.

Table 5. Recommended Operating Conditions (25 °C)

Switching Characteristics (25° C)

The timing diagram for both arrays, section 1 and section 2 are shown in Figure 5. Timing

Diagram for both Section 1 and Section 2.

Figure 5. Timing Diagram for both Section 1 and Section 2.

The switching characteristics for the I/O clocks are labeled symbolic acronyms for each

corresponding clock's switching edges. The corresponding times for these symbols are

given in the following Table 6.

Item

Symbol

Min.

Typical

Max.

Units

Clock cycle time

to

0.20

4.0

µs

Clock pulse width

tw

50

ns

Clock duty cycle

25

75

%

Prohibit crossing time

of Start Pulse

tprh

15

ns

Data setup time

tds

20

ns

Data hold time

tdh

20

ns

Signal delay time

tdl

50

ns

Signal settling time

tsh

120

ns

Table 6. Symbol Definitions for the Timing Diagram

CP

SP

tds

Vout

tsh

tdl

to

tw

tprh

tdh

PAGE 8 OF 9 - PI324MC-A4, 11-15-00

MODULE TIMING DIAGRAM