Data Sheet

AD5124/AD5144/AD5144A

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

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Rev. E | 16 of 37

Figure 10. 20-Lead TSSOP, I2C Interface Pin Configuration (AD5144A)

Table 11. 20-Lead TSSOP, I2C Interface Pin Function Descriptions (AD5144A)

Pin No.

Mnemonic

Description

1

RESET

Hardware Reset Pin. Refresh the RDAC registers from EEPROM. RESET is activated at the logic low. If this pin is not used, tie RESET to

VLOGIC.

2

GND

Ground Pin, Logic Ground Reference.

3

A1

Terminal A of RDAC1. VSS ≤ VA ≤ VDD.

4

W1

Wiper Terminal of RDAC1. VSS ≤ VW ≤ VDD.

5

B1

Terminal B of RDAC1. VSS ≤ VB ≤ VDD.

6

A3

Terminal A of RDAC3. VSS ≤ VA ≤ VDD.

7

W3

Wiper Terminal of RDAC3. VSS ≤ VW ≤ VDD.

8

B3

Terminal B of RDAC3. VSS ≤ VB ≤ VDD.

9

VSS

Negative Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

10

A2

Terminal A of RDAC2. VSS ≤ VA ≤ VDD.

11

W2

Wiper Terminal of RDAC2. VSS ≤ VW ≤ VDD.

12

B2

Terminal B of RDAC2. VSS ≤ VB ≤ VDD.

13

A4

Terminal A of RDAC4. VSS ≤ VA ≤ VDD.

14

W4

Wiper Terminal of RDAC4. VSS ≤ VW ≤ VDD.

15

B4

Terminal B of RDAC4. VSS ≤ VB ≤ VDD.

16

VDD

Positive Power Supply. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

17

VLOGIC

Logic Power Supply; 1.8 V to VDD. Decouple this pin with 0.1 µF ceramic capacitors and 10 µF capacitors.

18

SCL

Serial Clock Line. Data is clocked in at the logic low transition.

19

SDA

Serial Data Input/Output.

20

ADDR

Programmable Address for Multiple Package Decoding.