LD5762M datasheet(13/17 Pages) LEADTREND

13 / 17 page

LD5762M

09/25/2019

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5762M-DS-00 September 2019

more than 50%. To stabilize the control loop, the slope

compensation is required in the traditional UC384X

design by injecting the ramp signal from the RT/CT pin

through a coupling capacitor. LD5762M has internal

slope compensation circuit to simplify the external circuit

design.

Oscillator and Switching Frequency

The LD5762M has the switching frequency between 65

kHz ±4kHz internally to optimize its performance in EMI,

thermal treatment, component sizes and transformer

design.

Dual-Oscillator Green-Mode Operation

Many different topologies have been implemented in

different chips for the green-mode or power saving

requirements

such

“burst-mode

control

”,

“skipping-cycle mode”, “variable off-time control “…etc.

The basic operation theory of all these approaches

intended to reduce the switching cycles under light-load

or no-load condition either by skipping some switching

pulses or reducing the switching frequency.

By using LD proprietary dual-oscillator technique, the

green-mode frequency can be well controlled and

further to avoid the generation of audible noise.

On/Off Control

Pulling COMP pin below VZDC will immediately disable

the gate output of LD5762M. Remove the pull-low signal

to reset it.

Over Current Protection (OCP) - Auto

Recovery

Auto recovery of smart OCP protection is the feature of

LD5762M. Fig. 13 shows the waveform under fault

condition. The feedback system will force the voltage

loop toward the saturation and thus pull the voltage high

across COMP pin (VCOMP). When the VCOMP ramps

up and achieves the OCP threshold of 4.6V, staying for

longer than OCP delay time, the protection will be

activated. The delay time prevents the false-triggering

during power-on, turn-off transient.

VCC

UVLO(ON)

UVLO(OFF)

COMP

OCP

VOCP

OUT

OCP Delay Time

Switching

Non-Switching

OCP trip Level

2nd UVLO(OFF)

OCP Counter Reset

BNO

Detecting

Fig. 13

Over Voltage Protection on VCC (OVP)

–

Latch Mode

The VGS ratings of the nowadays power MOSFETs are

mostly with 28.5V maximum. To protect the VGS from

the fault condition, LD5762M is implemented with OVP

function on VCC. As the VCC voltage is larger than the

OVP threshold voltage, the output gate drive circuit will

be shut off simultaneously and stop switching the power

MOSFET.

The VCC OVP is latch-off type of protection. Once the

VCC trips OVP level (which is usually caused by the

feedback loop opened), it will be latched off and try to

recover. Turn off AC power to let VCC fall below PDR

level to release overvoltage protection. Then, restart the

power to resume the operation. The de-latch level is

defined by internal PDR. See Fig. 14 for its operation.

LD5762M Datasheet(PDF) 13 Page - Leadtrend Technology

LD5762M Datasheet(HTML) 13 Page - Leadtrend Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Datasheet Download

Link URL