AM79M535 datasheet(11/18 Pages) AMD

11 / 18 page

SLIC Products

Notes:

1. Unless otherwise noted, test conditions are BAT = –48 V, VCC = +5 V, VEE = –5 V, RL = 600 Ω, CHP = 0.22 µF,

RDC1 = RDC2 = 31.25 kΩ, CDC = 0.1 µF, Rd = 51.1 kΩ, no fuse resistors, two-wire AC output impedance, programming

impedance (ZT)= 306 kΩ resistive, receive input summing impedance (ZRX) = 300 kΩ resistive. (See Table 2 for compo-

nent formulas.)

2. Overload level is defined when THD = 1%.

3. Balance return signal is the signal generated at VTX by VRX. This specification assumes that the two-wire AC load impedance

matches the impedance programmed by ZT.

4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.

5. These tests are performed with a longitudinal impedance of 90

Ω and metallic impedance of 300 Ω for frequencies below

12 kHz and 135

Ω for frequencies greater than 12 kHz. These tests are extremely sensitive to circuit board layout.

6. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.

7. When the SLIC is in the Anti-sat 2 operating region, this parameter is degraded. The exact degradation depends on system

design. The Anti-sat 2 region occurs at high loop resistances when

V

BAT – VAX – VBX is less than approximately 17 V.

8. “Midpoint” is defined as the connection point between two 300

Ω series resistors connected between A(TIP) and B(RING).

9. Fundamental and harmonics from 256 kHz switch-regulator chopper are not included.

10. Total harmonic distortion with metering as specified with a metering signal of 2.2 Vrms at the two-wire output, and a transmit

signal of +3 dBm or receive signal of –4 dBm. The transmit or receive signals are single-frequency inputs, and the distortion

is measured as the highest in-band harmonic at the two-wire or the four-wire output relative to the input signal.

11. Noise with metering is measured by applying a 2.2 Vrms metering signal (measured at the two-wire output) and measuring

the psophometric noise at the two-wire and four-wire outputs over a 200 ms time interval.

12. Tested with 0

Ω source impedance. 2 MΩ is specified for system design purposes only.

13. Assumes the following ZT network:

14. Group delay can be considerably reduced by using a ZT network such as that shown in Note 13 above. The network reduces

the group delay to less than 2

µs. The effect of group delay on linecard performance may be compensated for by using the

QSLAC™ or DSLAC™ devices.

Note:

* A logic Low on E0 disables the DET output into the open-collector state.

Table 1.

SLIC Decoding

DET Output

State

C3 C2 C1

Two-Wire Status

E0 = 1*

E1 = 0

E0 = 1*

E1 = 1

Open Circuit

Ring trip

Ringing

Ring trip

Active

Loop detector

Ground key

On-hook TX (OHT)

Loop detector

Ground key

Tip Open

Loop detector

—

Reserved

Loop detector

—

Active Polarity Reversal

Loop detector

Ground key

OHT Polarity Reversal

Loop detector

Ground key

VTX

RSN

153 k

Ω

153 k

Ω

56 pF

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